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-- ------------------------------------------------------------------------
-- Copyright (C) 2005 Arif Endro Nugroho
-- All rights reserved.
-- 
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 
-- 1. Redistributions of source code must retain the above copyright
--    notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
--    notice, this list of conditions and the following disclaimer in the
--    documentation and/or other materials provided with the distribution.
-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote
--    products derived from this software without specific prior written
--    permission.
-- 
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-- 
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity mini_aes is
  port (
    clock  : in  std_logic;
    clear  : in  std_logic;
    load_i : in  std_logic;
    enc    : in  std_logic;             -- active low (e.g. 0 = encrypt, 1 = decrypt)
    key_i  : in  std_logic_vector (7 downto 0);
    data_i : in  std_logic_vector (7 downto 0);
    data_o : out std_logic_vector (7 downto 0);
    done_o : out std_logic
    );
end mini_aes;
 
architecture data_flow of mini_aes is
 
  component io_interface
    port (
      clock      : in  std_logic;
      clear      : in  std_logic;
      load_i     : in  std_logic;
      load_i_int : out std_logic;
      data_i     : in  std_logic_vector (7 downto 0);
      key_i      : in  std_logic_vector (7 downto 0);
      data_o     : out std_logic_vector (7 downto 0);
      data_o_int : in  std_logic_vector (127 downto 000);
      data_i_int : out std_logic_vector (127 downto 000);
      key_i_int  : out std_logic_vector (127 downto 000);
      done_o_int : in  std_logic;
      done_o     : out std_logic
      );
  end component;
 
  component bram_block_a
    port (
      clk_a_i     : in  std_logic;
      en_a_i      : in  std_logic;
      we_a_i      : in  std_logic;
      di_a_i      : in  std_logic_vector (07 downto 00);
      addr_a_1_i  : in  std_logic_vector (08 downto 00);
      addr_a_2_i  : in  std_logic_vector (08 downto 00);
      do_a_1_o    : out std_logic_vector (07 downto 00);
      do_a_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component bram_block_b
    port (
      clk_b_i     : in  std_logic;
      we_b_i      : in  std_logic;
      en_b_i      : in  std_logic;
      di_b_i      : in  std_logic_vector (07 downto 00);
      addr_b_1_i  : in  std_logic_vector (08 downto 00);
      addr_b_2_i  : in  std_logic_vector (08 downto 00);
      do_b_1_o    : out std_logic_vector (07 downto 00);
      do_b_2_o    : out std_logic_vector (07 downto 00)
      );
  end component;
--
  component mix_column
    port (
      s0          : in  std_logic_vector (07 downto 00);
      s1          : in  std_logic_vector (07 downto 00);
      s2          : in  std_logic_vector (07 downto 00);
      s3          : in  std_logic_vector (07 downto 00);
      mix_col     : out std_logic_vector (31 downto 00);
      inv_mix_col : out std_logic_vector (31 downto 00)
      );
  end component;
--
  component key_scheduler
    port (
      clock       : in  std_logic;
      load        : in  std_logic;
      key_i       : in  std_logic_vector (127 downto 000);
      key_o       : out std_logic_vector (031 downto 000);
      done        : out std_logic
      );
  end component;
--
  component counter2bit
    port (
      clock       : in  std_logic;
      clear       : in  std_logic;
      count       : out std_logic_vector (1 downto 0)
      );
  end component;
--
  component folded_register
    port (
      clk_i       : in  std_logic;
      enc_i       : in  std_logic;
      load_i      : in  std_logic;
      data_i      : in  std_logic_vector (127 downto 000);
      key_i       : in  std_logic_vector (127 downto 000);
      di_0_i      : in  std_logic_vector (007 downto 000);
      di_1_i      : in  std_logic_vector (007 downto 000);
      di_2_i      : in  std_logic_vector (007 downto 000);
      di_3_i      : in  std_logic_vector (007 downto 000);
      do_0_o      : out std_logic_vector (007 downto 000);
      do_1_o      : out std_logic_vector (007 downto 000);
      do_2_o      : out std_logic_vector (007 downto 000);
      do_3_o      : out std_logic_vector (007 downto 000)
      );
  end component;
 
  type state        is array (03 downto 00) of std_logic_vector (07 downto 00);
  type allround     is array (43 downto 00) of std_logic_vector (31 downto 00);
  type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);
  signal   input            : state                             := ( X"00", X"00", X"00", X"00");
  signal   key_o_srl1_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl4_p     : partialround                      :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl1       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl2       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
  signal   key_o_srl3       : allround                          :=
    (
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000",
      X"00000000", X"00000000", X"00000000", X"00000000"
      );
--
  signal   counter          : std_logic_vector (01 downto 00)     := "00";
  signal   inner_round      : std_logic                           := '0';
  signal   key_counter_up   : integer range 0 to 43;
  signal   key_counter_down : integer range 0 to 43;
  signal   done             : std_logic                           := '0';
  signal   done_decrypt     : std_logic                           := '0';
  signal   counter1bit      : std_logic                           := '0';
  signal   done_o_int       : std_logic                           := '0';
  signal   data_i_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   data_o_int       : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_i_int        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   load             : std_logic                           := '0';
  signal   load_io          : std_logic                           := '0';
  signal   di_0_i           : std_logic_vector (007 downto 000);
  signal   di_1_i           : std_logic_vector (007 downto 000);
  signal   di_2_i           : std_logic_vector (007 downto 000);
  signal   di_3_i           : std_logic_vector (007 downto 000);
  signal   do_0_o           : std_logic_vector (007 downto 000);
  signal   do_1_o           : std_logic_vector (007 downto 000);
  signal   do_2_o           : std_logic_vector (007 downto 000);
  signal   do_3_o           : std_logic_vector (007 downto 000);
  signal   current_key      : std_logic_vector (031 downto 000)   := ( X"0000_0000");
  signal   output_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   output           : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   key_o            : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   fifo16x8         : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8i        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   fifo16x8o        : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  signal   key_b            : std_logic_vector (127 downto 000)   := ( X"00000000_00000000_00000000_00000000" );
  constant GND              : std_logic                           := '0';
  constant VCC              : std_logic                           := '1';
 
  signal   mixcol_s0_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s1_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s2_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_s3_i      : std_logic_vector (007 downto 000)   := B"0000_0000";
  signal   mixcol_o         : std_logic_vector (031 downto 000)   := ( X"00000000" );
  signal   inv_mixcol_o     : std_logic_vector (031 downto 000)   := ( X"00000000" );
--
  signal   en_a_i           : std_logic;
  signal   en_b_i           : std_logic;
  signal   clk_a_i          : std_logic;
  signal   clk_b_i          : std_logic;
  signal   we_a_i           : std_logic;
  signal   we_b_i           : std_logic;
  signal   di_a_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   di_b_i           : std_logic_vector (07 downto 00)   := B"0000_0000";
  signal   addr_a_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_a_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_1_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   addr_b_2_i       : std_logic_vector (08 downto 00)   := B"0_0000_0000";
  signal   do_a_1_o         : std_logic_vector (07 downto 00);
  signal   do_a_2_o         : std_logic_vector (07 downto 00);
  signal   do_b_1_o         : std_logic_vector (07 downto 00);
  signal   do_b_2_o         : std_logic_vector (07 downto 00);
 
--signal data_i_int : std_logic_vector (127 downto 000) :=
--( X"3243F6A8_885A308D_313198A2_E0370734" );  -- PT 0
--( X"00112233_44556677_8899AABB_CCDDEEFF" );  -- PT 1
--( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" );  -- CT 1
--signal key_i : std_logic_vector (127 downto 000) :=
--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" );  -- KEY 0
--( X"00010203_04050607_08090A0B_0C0D0E0F" );  -- KEY 1
 
begin
 
  clk_a_i <= clock;
  clk_b_i <= clock;
  en_a_i  <= VCC;
  en_b_i  <= VCC;
  we_a_i  <= GND;
  we_b_i  <= GND;
 
  done_o_int <= done_decrypt;
 
  my_io : io_interface
    port map (
      clock      => clock,
      clear      => clear,
      load_i     => load_i,
      load_i_int => load_io,
      data_i     => data_i,
      key_i      => key_i,
      data_o     => data_o,
      data_o_int => data_o_int,
      data_i_int => data_i_int,
      key_i_int  => key_i_int,
      done_o_int => done_o_int,
      done_o     => done_o
      );
 
  sbox1     : bram_block_a
    port map (
      clk_a_i     => clk_a_i,
      en_a_i      => en_a_i,
      we_a_i      => we_a_i,
      di_a_i      => di_a_i,
      addr_a_1_i  => addr_a_1_i,
      addr_a_2_i  => addr_a_2_i,
      do_a_1_o    => do_a_1_o,
      do_a_2_o    => do_a_2_o
      );
--
  sbox2     : bram_block_b
    port map (
      clk_b_i     => clk_b_i,
      we_b_i      => we_b_i,
      en_b_i      => en_b_i,
      di_b_i      => di_b_i,
      addr_b_1_i  => addr_b_1_i,
      addr_b_2_i  => addr_b_2_i,
      do_b_1_o    => do_b_1_o,
      do_b_2_o    => do_b_2_o
      );
--
  mixcol    : mix_column
    port map (
      s0          => mixcol_s0_i,
      s1          => mixcol_s1_i,
      s2          => mixcol_s2_i,
      s3          => mixcol_s3_i,
      mix_col     => mixcol_o,
      inv_mix_col => inv_mixcol_o
      );
--
  key       : key_scheduler
    port map (
      clock       => clock,
      load        => load,
      key_i       => key_i_int,
      key_o       => key_o,
      done        => done
      );
--
  count2bit : counter2bit
    port map (
      clock       => clock,
      clear       => load,
      count       => counter
      );
--
  foldreg   : folded_register
    port map (
      clk_i       => clock,
      enc_i       => enc,
      load_i      => load,
      data_i      => data_i_int,
      key_i       => key_b,
      di_0_i      => di_0_i,
      di_1_i      => di_1_i,
      di_2_i      => di_2_i,
      di_3_i      => di_3_i,
      do_0_o      => do_0_o,
      do_1_o      => do_1_o,
      do_2_o      => do_2_o,
      do_3_o      => do_3_o
      );
 
  process(clock, clear)
  begin
    if (clear = '1') then
      load                        <= '1';
    elsif (clock = '1' and clock'event) then
      fifo16x8 (127 downto 000)   <= fifo16x8i (127 downto 000);
      if (done = '1') then
        load                      <= '1';
      else
--      load                      <= '0';
        load                      <= load_io;
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1                  <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      if (inner_round = '1') then
        key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);
      end if;
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl1_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);
    end if;
  end process;
--
  process(clear, clock)
  begin
    if (clear = '1') then
      key_o_srl3_p                <= (others => (others => '0'));
    elsif (clock = '1' and clock'event) then
      key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);
    end if;
  end process;
 
  key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);
  key_o_srl2_p (00)           <= key_o;
  key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);
  key_o_srl4_p (03)           <= key_o;
--
  inner_round <= ( counter(1) and counter(0) );
--
  key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);
 
  key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
                               ( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
 
  key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
                                 key_i_int (127 downto 096) &
                                 key_i_int (095 downto 064) &
                                 key_i_int (063 downto 032) &
                                 key_i_int (031 downto 000)
                               ) when (done = '1') else
                                 key_o_srl3 (43 downto 00);
 
  fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
  fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
 
  data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);
--
  input (0)               <= do_0_o;
  input (1)               <= do_1_o;
  input (2)               <= do_2_o;
  input (3)               <= do_3_o;
--
  addr_a_1_i              <= (enc & input(0));
  addr_a_2_i              <= (enc & input(1));
  addr_b_1_i              <= (enc & input(2));
  addr_b_2_i              <= (enc & input(3));
--
  mixcol_s0_i             <= do_a_1_o when (enc = '0') else output (31 downto 24);
  mixcol_s1_i             <= do_a_2_o when (enc = '0') else output (23 downto 16);
  mixcol_s2_i             <= do_b_1_o when (enc = '0') else output (15 downto 08);
  mixcol_s3_i             <= do_b_2_o when (enc = '0') else output (07 downto 00);
 
  output   <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else
              (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);
 
  di_0_i                 <= output (31 downto 24)  when (enc = '0') else inv_mixcol_o (31 downto 24);
  di_1_i                 <= output (23 downto 16)  when (enc = '0') else inv_mixcol_o (23 downto 16);
  di_2_i                 <= output (15 downto 08)  when (enc = '0') else inv_mixcol_o (15 downto 08);
  di_3_i                 <= output (07 downto 00)  when (enc = '0') else inv_mixcol_o (07 downto 00);
--
  key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
 
  current_key <= key_o_srl3(key_counter_down);
 
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_up     <= 4;
    elsif (clock = '1' and clock'event) then
      if (key_counter_up < 43) then
        key_counter_up   <= key_counter_up + 1;
      else
        key_counter_up   <= 4;
      end if;
    end if;
  end process;
--
  process (clock, load)
  begin
    if (load = '1') then
      key_counter_down   <= 39;
    elsif (clock = '1' and clock'event) then
      if (key_counter_down > 0) then
        key_counter_down <= key_counter_down - 1;
      else
        key_counter_down <= 39;
      end if;
    end if;
  end process;
--
  process(clear, done)
  begin
    if (clear = '1') then
      counter1bit        <= '0';
    elsif (done = '1' and done'event) then
      counter1bit        <= not (counter1bit);
    end if;
  end process;
--
  process (load, counter1bit)
  begin
    if (load = '1') then
      done_decrypt       <= '0';
    elsif (counter1bit = '0' and counter1bit'event) then
      done_decrypt       <= '1';
    end if;
  end process;
 
end data_flow;

Line No.	Rev	Author	Line
1	21	arif_endro	`-- ------------------------------------------------------------------------`
2	15	arif_endro	`-- Copyright (C) 2005 Arif Endro Nugroho`
3	21	arif_endro	`-- All rights reserved.`
4	2	arif_endro	`--`
5	21	arif_endro	`-- Redistribution and use in source and binary forms, with or without`
6			`-- modification, are permitted provided that the following conditions`
7			`-- are met:`
8	2	arif_endro	`--`
9	21	arif_endro	`-- 1. Redistributions of source code must retain the above copyright`
10			`-- notice, this list of conditions and the following disclaimer.`
11			`-- 2. Redistributions in binary form must reproduce the above copyright`
12			`-- notice, this list of conditions and the following disclaimer in the`
13			`-- documentation and/or other materials provided with the distribution.`
14			`-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote`
15			`-- products derived from this software without specific prior written`
16			`-- permission.`
17	2	arif_endro	`--`
18	21	arif_endro	`-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS`
19			`-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
20			`-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
21			`-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY`
22			`-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
24			`-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
25			`-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
26			`-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN`
27			`-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
28			`-- POSSIBILITY OF SUCH DAMAGE.`
29	2	arif_endro	`--`
30	21	arif_endro	`-- End Of License.`
31			`-- ------------------------------------------------------------------------`
32	2	arif_endro
33			`library ieee;`
34			`use ieee.std_logic_1164.all;`
35			`use ieee.std_logic_unsigned.all;`
36
37			`entity mini_aes is`
38			`port (`
39			`clock : in std_logic;`
40			`clear : in std_logic;`
41	5	arif_endro	`load_i : in std_logic;`
42	2	arif_endro	`enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)`
43	5	arif_endro	`key_i : in std_logic_vector (7 downto 0);`
44			`data_i : in std_logic_vector (7 downto 0);`
45			`data_o : out std_logic_vector (7 downto 0);`
46	2	arif_endro	`done_o : out std_logic`
47			`);`
48			`end mini_aes;`
49
50			`architecture data_flow of mini_aes is`
51
52	5	arif_endro	`component io_interface`
53			`port (`
54			`clock : in std_logic;`
55			`clear : in std_logic;`
56			`load_i : in std_logic;`
57			`load_i_int : out std_logic;`
58			`data_i : in std_logic_vector (7 downto 0);`
59			`key_i : in std_logic_vector (7 downto 0);`
60			`data_o : out std_logic_vector (7 downto 0);`
61			`data_o_int : in std_logic_vector (127 downto 000);`
62			`data_i_int : out std_logic_vector (127 downto 000);`
63			`key_i_int : out std_logic_vector (127 downto 000);`
64			`done_o_int : in std_logic;`
65			`done_o : out std_logic`
66			`);`
67			`end component;`
68
69	2	arif_endro	`component bram_block_a`
70			`port (`
71			`clk_a_i : in std_logic;`
72			`en_a_i : in std_logic;`
73			`we_a_i : in std_logic;`
74			`di_a_i : in std_logic_vector (07 downto 00);`
75			`addr_a_1_i : in std_logic_vector (08 downto 00);`
76			`addr_a_2_i : in std_logic_vector (08 downto 00);`
77			`do_a_1_o : out std_logic_vector (07 downto 00);`
78			`do_a_2_o : out std_logic_vector (07 downto 00)`
79			`);`
80			`end component;`
81			`--`
82			`component bram_block_b`
83			`port (`
84			`clk_b_i : in std_logic;`
85			`we_b_i : in std_logic;`
86			`en_b_i : in std_logic;`
87			`di_b_i : in std_logic_vector (07 downto 00);`
88			`addr_b_1_i : in std_logic_vector (08 downto 00);`
89			`addr_b_2_i : in std_logic_vector (08 downto 00);`
90			`do_b_1_o : out std_logic_vector (07 downto 00);`
91			`do_b_2_o : out std_logic_vector (07 downto 00)`
92			`);`
93			`end component;`
94			`--`
95			`component mix_column`
96			`port (`
97			`s0 : in std_logic_vector (07 downto 00);`
98			`s1 : in std_logic_vector (07 downto 00);`
99			`s2 : in std_logic_vector (07 downto 00);`
100			`s3 : in std_logic_vector (07 downto 00);`
101			`mix_col : out std_logic_vector (31 downto 00);`
102			`inv_mix_col : out std_logic_vector (31 downto 00)`
103			`);`
104			`end component;`
105			`--`
106			`component key_scheduler`
107			`port (`
108			`clock : in std_logic;`
109			`load : in std_logic;`
110			`key_i : in std_logic_vector (127 downto 000);`
111			`key_o : out std_logic_vector (031 downto 000);`
112			`done : out std_logic`
113			`);`
114			`end component;`
115			`--`
116			`component counter2bit`
117			`port (`
118			`clock : in std_logic;`
119			`clear : in std_logic;`
120			`count : out std_logic_vector (1 downto 0)`
121			`);`
122			`end component;`
123			`--`
124			`component folded_register`
125			`port (`
126			`clk_i : in std_logic;`
127			`enc_i : in std_logic;`
128			`load_i : in std_logic;`
129			`data_i : in std_logic_vector (127 downto 000);`
130			`key_i : in std_logic_vector (127 downto 000);`
131			`di_0_i : in std_logic_vector (007 downto 000);`
132			`di_1_i : in std_logic_vector (007 downto 000);`
133			`di_2_i : in std_logic_vector (007 downto 000);`
134			`di_3_i : in std_logic_vector (007 downto 000);`
135			`do_0_o : out std_logic_vector (007 downto 000);`
136			`do_1_o : out std_logic_vector (007 downto 000);`
137			`do_2_o : out std_logic_vector (007 downto 000);`
138			`do_3_o : out std_logic_vector (007 downto 000)`
139			`);`
140			`end component;`
141
142			`type state is array (03 downto 00) of std_logic_vector (07 downto 00);`
143			`type allround is array (43 downto 00) of std_logic_vector (31 downto 00);`
144			`type partialround is array (03 downto 00) of std_logic_vector (31 downto 00);`
145			`signal input : state := ( X"00", X"00", X"00", X"00");`
146			`signal key_o_srl1_p : partialround :=`
147			`(`
148			`X"00000000", X"00000000", X"00000000", X"00000000"`
149			`);`
150			`signal key_o_srl2_p : partialround :=`
151			`(`
152			`X"00000000", X"00000000", X"00000000", X"00000000"`
153			`);`
154			`signal key_o_srl3_p : partialround :=`
155			`(`
156			`X"00000000", X"00000000", X"00000000", X"00000000"`
157			`);`
158			`signal key_o_srl4_p : partialround :=`
159			`(`
160			`X"00000000", X"00000000", X"00000000", X"00000000"`
161			`);`
162			`signal key_o_srl1 : allround :=`
163			`(`
164			`X"00000000", X"00000000", X"00000000", X"00000000",`
165			`X"00000000", X"00000000", X"00000000", X"00000000",`
166			`X"00000000", X"00000000", X"00000000", X"00000000",`
167			`X"00000000", X"00000000", X"00000000", X"00000000",`
168			`X"00000000", X"00000000", X"00000000", X"00000000",`
169			`X"00000000", X"00000000", X"00000000", X"00000000",`
170			`X"00000000", X"00000000", X"00000000", X"00000000",`
171			`X"00000000", X"00000000", X"00000000", X"00000000",`
172			`X"00000000", X"00000000", X"00000000", X"00000000",`
173			`X"00000000", X"00000000", X"00000000", X"00000000",`
174			`X"00000000", X"00000000", X"00000000", X"00000000"`
175			`);`
176			`signal key_o_srl2 : allround :=`
177			`(`
178			`X"00000000", X"00000000", X"00000000", X"00000000",`
179			`X"00000000", X"00000000", X"00000000", X"00000000",`
180			`X"00000000", X"00000000", X"00000000", X"00000000",`
181			`X"00000000", X"00000000", X"00000000", X"00000000",`
182			`X"00000000", X"00000000", X"00000000", X"00000000",`
183			`X"00000000", X"00000000", X"00000000", X"00000000",`
184			`X"00000000", X"00000000", X"00000000", X"00000000",`
185			`X"00000000", X"00000000", X"00000000", X"00000000",`
186			`X"00000000", X"00000000", X"00000000", X"00000000",`
187			`X"00000000", X"00000000", X"00000000", X"00000000",`
188			`X"00000000", X"00000000", X"00000000", X"00000000"`
189			`);`
190			`signal key_o_srl3 : allround :=`
191			`(`
192			`X"00000000", X"00000000", X"00000000", X"00000000",`
193			`X"00000000", X"00000000", X"00000000", X"00000000",`
194			`X"00000000", X"00000000", X"00000000", X"00000000",`
195			`X"00000000", X"00000000", X"00000000", X"00000000",`
196			`X"00000000", X"00000000", X"00000000", X"00000000",`
197			`X"00000000", X"00000000", X"00000000", X"00000000",`
198			`X"00000000", X"00000000", X"00000000", X"00000000",`
199			`X"00000000", X"00000000", X"00000000", X"00000000",`
200			`X"00000000", X"00000000", X"00000000", X"00000000",`
201			`X"00000000", X"00000000", X"00000000", X"00000000",`
202			`X"00000000", X"00000000", X"00000000", X"00000000"`
203			`);`
204			`--`
205			`signal counter : std_logic_vector (01 downto 00) := "00";`
206			`signal inner_round : std_logic := '0';`
207			`signal key_counter_up : integer range 0 to 43;`
208			`signal key_counter_down : integer range 0 to 43;`
209			`signal done : std_logic := '0';`
210			`signal done_decrypt : std_logic := '0';`
211			`signal counter1bit : std_logic := '0';`
212	5	arif_endro	`signal done_o_int : std_logic := '0';`
213			`signal data_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
214			`signal data_o_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
215			`signal key_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
216	2	arif_endro	`signal load : std_logic := '0';`
217	5	arif_endro	`signal load_io : std_logic := '0';`
218	2	arif_endro	`signal di_0_i : std_logic_vector (007 downto 000);`
219			`signal di_1_i : std_logic_vector (007 downto 000);`
220			`signal di_2_i : std_logic_vector (007 downto 000);`
221			`signal di_3_i : std_logic_vector (007 downto 000);`
222			`signal do_0_o : std_logic_vector (007 downto 000);`
223			`signal do_1_o : std_logic_vector (007 downto 000);`
224			`signal do_2_o : std_logic_vector (007 downto 000);`
225			`signal do_3_o : std_logic_vector (007 downto 000);`
226			`signal current_key : std_logic_vector (031 downto 000) := ( X"0000_0000");`
227			`signal output_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
228			`signal output : std_logic_vector (031 downto 000) := ( X"00000000" );`
229			`signal key_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
230			`signal fifo16x8 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
231			`signal fifo16x8i : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
232			`signal fifo16x8o : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
233			`signal key_b : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );`
234			`constant GND : std_logic := '0';`
235			`constant VCC : std_logic := '1';`
236
237			`signal mixcol_s0_i : std_logic_vector (007 downto 000) := B"0000_0000";`
238			`signal mixcol_s1_i : std_logic_vector (007 downto 000) := B"0000_0000";`
239			`signal mixcol_s2_i : std_logic_vector (007 downto 000) := B"0000_0000";`
240			`signal mixcol_s3_i : std_logic_vector (007 downto 000) := B"0000_0000";`
241			`signal mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
242			`signal inv_mixcol_o : std_logic_vector (031 downto 000) := ( X"00000000" );`
243			`--`
244			`signal en_a_i : std_logic;`
245			`signal en_b_i : std_logic;`
246			`signal clk_a_i : std_logic;`
247			`signal clk_b_i : std_logic;`
248			`signal we_a_i : std_logic;`
249			`signal we_b_i : std_logic;`
250			`signal di_a_i : std_logic_vector (07 downto 00) := B"0000_0000";`
251			`signal di_b_i : std_logic_vector (07 downto 00) := B"0000_0000";`
252			`signal addr_a_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
253			`signal addr_a_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
254			`signal addr_b_1_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
255			`signal addr_b_2_i : std_logic_vector (08 downto 00) := B"0_0000_0000";`
256			`signal do_a_1_o : std_logic_vector (07 downto 00);`
257			`signal do_a_2_o : std_logic_vector (07 downto 00);`
258			`signal do_b_1_o : std_logic_vector (07 downto 00);`
259			`signal do_b_2_o : std_logic_vector (07 downto 00);`
260
261	5	arif_endro	`--signal data_i_int : std_logic_vector (127 downto 000) :=`
262	2	arif_endro	`--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0`
263			`--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1`
264			`--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0`
265			`--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1`
266			`--signal key_i : std_logic_vector (127 downto 000) :=`
267			`--( X"2B7E1516_28AED2A6_ABF71588_09CF4F3C" ); -- KEY 0`
268			`--( X"00010203_04050607_08090A0B_0C0D0E0F" ); -- KEY 1`
269
270			`begin`
271
272			`clk_a_i <= clock;`
273			`clk_b_i <= clock;`
274			`en_a_i <= VCC;`
275			`en_b_i <= VCC;`
276			`we_a_i <= GND;`
277			`we_b_i <= GND;`
278
279	5	arif_endro	`done_o_int <= done_decrypt;`
280	2	arif_endro
281	5	arif_endro	`my_io : io_interface`
282			`port map (`
283			`clock => clock,`
284			`clear => clear,`
285			`load_i => load_i,`
286			`load_i_int => load_io,`
287			`data_i => data_i,`
288			`key_i => key_i,`
289			`data_o => data_o,`
290			`data_o_int => data_o_int,`
291			`data_i_int => data_i_int,`
292			`key_i_int => key_i_int,`
293			`done_o_int => done_o_int,`
294			`done_o => done_o`
295			`);`
296
297	2	arif_endro	`sbox1 : bram_block_a`
298			`port map (`
299			`clk_a_i => clk_a_i,`
300			`en_a_i => en_a_i,`
301			`we_a_i => we_a_i,`
302			`di_a_i => di_a_i,`
303			`addr_a_1_i => addr_a_1_i,`
304			`addr_a_2_i => addr_a_2_i,`
305			`do_a_1_o => do_a_1_o,`
306			`do_a_2_o => do_a_2_o`
307			`);`
308			`--`
309			`sbox2 : bram_block_b`
310			`port map (`
311			`clk_b_i => clk_b_i,`
312			`we_b_i => we_b_i,`
313			`en_b_i => en_b_i,`
314			`di_b_i => di_b_i,`
315			`addr_b_1_i => addr_b_1_i,`
316			`addr_b_2_i => addr_b_2_i,`
317			`do_b_1_o => do_b_1_o,`
318			`do_b_2_o => do_b_2_o`
319			`);`
320			`--`
321			`mixcol : mix_column`
322			`port map (`
323			`s0 => mixcol_s0_i,`
324			`s1 => mixcol_s1_i,`
325			`s2 => mixcol_s2_i,`
326			`s3 => mixcol_s3_i,`
327			`mix_col => mixcol_o,`
328			`inv_mix_col => inv_mixcol_o`
329			`);`
330			`--`
331			`key : key_scheduler`
332			`port map (`
333			`clock => clock,`
334			`load => load,`
335	5	arif_endro	`key_i => key_i_int,`
336	2	arif_endro	`key_o => key_o,`
337			`done => done`
338			`);`
339			`--`
340			`count2bit : counter2bit`
341			`port map (`
342			`clock => clock,`
343			`clear => load,`
344			`count => counter`
345			`);`
346			`--`
347			`foldreg : folded_register`
348			`port map (`
349			`clk_i => clock,`
350			`enc_i => enc,`
351			`load_i => load,`
352	5	arif_endro	`data_i => data_i_int,`
353	2	arif_endro	`key_i => key_b,`
354			`di_0_i => di_0_i,`
355			`di_1_i => di_1_i,`
356			`di_2_i => di_2_i,`
357			`di_3_i => di_3_i,`
358			`do_0_o => do_0_o,`
359			`do_1_o => do_1_o,`
360			`do_2_o => do_2_o,`
361			`do_3_o => do_3_o`
362			`);`
363
364			`process(clock, clear)`
365			`begin`
366			`if (clear = '1') then`
367			`load <= '1';`
368			`elsif (clock = '1' and clock'event) then`
369			`fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);`
370			`if (done = '1') then`
371			`load <= '1';`
372			`else`
373	5	arif_endro	`-- load <= '0';`
374			`load <= load_io;`
375	2	arif_endro	`end if;`
376			`end if;`
377			`end process;`
378			`--`
379			`process(clear, clock)`
380			`begin`
381			`if (clear = '1') then`
382			`key_o_srl1 <= (others => (others => '0'));`
383			`elsif (clock = '1' and clock'event) then`
384			`if (inner_round = '1') then`
385			`key_o_srl1 (43 downto 00) <= key_o_srl2 (43 downto 00);`
386			`end if;`
387			`end if;`
388			`end process;`
389			`--`
390			`process(clear, clock)`
391			`begin`
392			`if (clear = '1') then`
393			`key_o_srl1_p <= (others => (others => '0'));`
394			`elsif (clock = '1' and clock'event) then`
395			`key_o_srl1_p (03 downto 00) <= key_o_srl2_p (03 downto 00);`
396			`end if;`
397			`end process;`
398			`--`
399			`process(clear, clock)`
400			`begin`
401			`if (clear = '1') then`
402			`key_o_srl3_p <= (others => (others => '0'));`
403			`elsif (clock = '1' and clock'event) then`
404			`key_o_srl3_p (03 downto 00) <= key_o_srl4_p (03 downto 00);`
405			`end if;`
406			`end process;`
407
408			`key_o_srl2_p (03 downto 01) <= key_o_srl1_p (02 downto 00);`
409			`key_o_srl2_p (00) <= key_o;`
410			`key_o_srl4_p (02 downto 00) <= key_o_srl3_p (03 downto 01);`
411			`key_o_srl4_p (03) <= key_o;`
412			`--`
413			`inner_round <= ( counter(1) and counter(0) );`
414			`--`
415			`key_o_srl2 (39 downto 00) <= key_o_srl1 (43 downto 04);`
416
417			`key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else`
418			`( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );`
419
420			`key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &`
421	5	arif_endro	`key_i_int (127 downto 096) &`
422			`key_i_int (095 downto 064) &`
423			`key_i_int (063 downto 032) &`
424			`key_i_int (031 downto 000)`
425	2	arif_endro	`) when (done = '1') else`
426			`key_o_srl3 (43 downto 00);`
427
428			`fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);`
429			`fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );`
430
431	5	arif_endro	`data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);`
432	2	arif_endro	`--`
433			`input (0) <= do_0_o;`
434			`input (1) <= do_1_o;`
435			`input (2) <= do_2_o;`
436			`input (3) <= do_3_o;`
437			`--`
438			`addr_a_1_i <= (enc & input(0));`
439			`addr_a_2_i <= (enc & input(1));`
440			`addr_b_1_i <= (enc & input(2));`
441			`addr_b_2_i <= (enc & input(3));`
442			`--`
443			`mixcol_s0_i <= do_a_1_o when (enc = '0') else output (31 downto 24);`
444			`mixcol_s1_i <= do_a_2_o when (enc = '0') else output (23 downto 16);`
445			`mixcol_s2_i <= do_b_1_o when (enc = '0') else output (15 downto 08);`
446			`mixcol_s3_i <= do_b_2_o when (enc = '0') else output (07 downto 00);`
447
448			`output <= mixcol_o xor key_o_srl3(key_counter_up) when (enc = '0') else`
449			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
450
451			`output_o <= (do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_up) when (enc = '0') else`
452			`(do_a_1_o & do_a_2_o & do_b_1_o & do_b_2_o) xor key_o_srl3(key_counter_down);`
453
454			`di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);`
455			`di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);`
456			`di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);`
457			`di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);`
458			`--`
459	5	arif_endro	`key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));`
460	2	arif_endro
461			`current_key <= key_o_srl3(key_counter_down);`
462
463			`process (clock, load)`
464			`begin`
465			`if (load = '1') then`
466			`key_counter_up <= 4;`
467			`elsif (clock = '1' and clock'event) then`
468			`if (key_counter_up < 43) then`
469			`key_counter_up <= key_counter_up + 1;`
470			`else`
471			`key_counter_up <= 4;`
472			`end if;`
473			`end if;`
474			`end process;`
475			`--`
476			`process (clock, load)`
477			`begin`
478			`if (load = '1') then`
479			`key_counter_down <= 39;`
480			`elsif (clock = '1' and clock'event) then`
481			`if (key_counter_down > 0) then`
482			`key_counter_down <= key_counter_down - 1;`
483			`else`
484			`key_counter_down <= 39;`
485			`end if;`
486			`end if;`
487			`end process;`
488			`--`
489			`process(clear, done)`
490			`begin`
491			`if (clear = '1') then`
492			`counter1bit <= '0';`
493			`elsif (done = '1' and done'event) then`
494			`counter1bit <= not (counter1bit);`
495			`end if;`
496			`end process;`
497			`--`
498			`process (load, counter1bit)`
499			`begin`
500			`if (load = '1') then`

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