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[/] [mini_aes/] [trunk/] [source/] [mix_column.vhdl] - Blame information for rev 20

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1 2 arif_endro
-- $Id: mix_column.vhdl,v 1.1.1.1 2005-12-06 02:48:33 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       :
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-- Project     : Mini AES 128 
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-------------------------------------------------------------------------------
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-- File        :
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2005/12/03
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-- Last update : 
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-- Simulators  : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : 
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.xtime_pkg.all;
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entity mix_column is
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  port (
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    s0          : in  std_logic_vector (07 downto 00);
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    s1          : in  std_logic_vector (07 downto 00);
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    s2          : in  std_logic_vector (07 downto 00);
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    s3          : in  std_logic_vector (07 downto 00);
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    mix_col     : out std_logic_vector (31 downto 00);
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    inv_mix_col : out std_logic_vector (31 downto 00)
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    );
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end mix_column;
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architecture data_flow of mix_column is
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  type state is array (03 downto 00) of std_logic_vector (07 downto 00);
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  signal mc : state :=
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    ( X"00", X"00", X"00", X"00" );
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begin
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  --
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  -- MixColumn   : a(x)  = {03}x^3 + {01}x^2 + {01}x + {02}
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  --
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  -- s'0c = | 02 03 01 01 | s0c
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  -- s'1c = | 01 02 03 01 | s1c
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  -- s'2c = | 01 01 02 03 | s2c
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  -- s'3c = | 03 01 01 02 | s3c
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  --
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  -- InvMixColumn: a'(x) = {0B}x^3 + {0D}x^2 + {09}x + {0E}
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  --               a'(x) = {03}x^3 + {01}x^2 + {01}x + {02} +
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  --                       {08}x^3 + {08}x^2 + {08}x + {08} +
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  --                                 {04}x^2 + {04}x
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  --  a(x) * a'(x)     = {01}
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  --  a(x) * {a'(x)}^2 = {01} * a'(x) = a'(x)
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  --         {a'(x)}^2 = {04}x^2 + {05}
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  --
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  --              | 05 00 04 00 |          | 0E 0B 0D 09 |   E = 14 = 1110 = 8 xor 4 xor 2 = 1000 xor 0100 xor 0010
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  --  {a'(x)}^2 = | 00 05 00 04 |  a'(x) = | 09 0E 0B 0D |   D = 13 = 1101 = 8 xor 4 xor 1 = 1000 xor 0100 xor 0001
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  --              | 04 00 05 00 |          | 0D 09 0E 0B |   B = 11 = 1011 = 8 xor 2 xor 1 = 1000 xor 0010 xor 0001
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  --              | 00 04 00 05 |          | 0B 0D 09 0E |   9 = 09 = 1001 = 8 xor 0 xor 1 = 1000 xor 0000 xor 0001
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  --
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  mc (3) <= xtime_2(s0) xor xtime_2(s1) xor s1 xor s2 xor s3;
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  mc (2) <= s0 xor xtime_2(s1) xor xtime_2(s2) xor s2 xor s3;
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  mc (1) <= s0 xor s1 xor xtime_2(s2) xor xtime_2(s3) xor s3;
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  mc (0) <= xtime_2(s0) xor s0 xor s1 xor s2 xor xtime_2(s3);
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--
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  mix_col <= (mc(3) & mc(2) & mc(1) & mc(0));
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-- 
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  inv_mix_col (31 downto 24) <= xtime_4(mc(3)) xor mc(3) xor xtime_4(mc(1));
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  inv_mix_col (23 downto 16) <= xtime_4(mc(2)) xor mc(2) xor xtime_4(mc(0));
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  inv_mix_col (15 downto 08) <= xtime_4(mc(1)) xor mc(1) xor xtime_4(mc(3));
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  inv_mix_col (07 downto 00) <= xtime_4(mc(0)) xor mc(0) xor xtime_4(mc(2));
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--
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--   inv_mix_col (31 downto 24) <= 
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--                                 xtime_8(mc(3)) xor xtime_4(mc(3)) xor xtime_2(mc(3)) xor 
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--                                 xtime_8(mc(2)) xor xtime_2(mc(2)) xor mc(2) xor
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--                                 xtime_8(mc(1)) xor xtime_4(mc(1)) xor mc(1) xor
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--                                 xtime_8(mc(0)) xor mc(0);
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--   inv_mix_col (23 downto 16) <= 
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--                                 xtime_8(mc(3)) xor mc(3) xor
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--                                 xtime_8(mc(2)) xor xtime_4(mc(2)) xor xtime_2(mc(2)) xor 
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--                                 xtime_8(mc(1)) xor xtime_2(mc(1)) xor mc(1) xor
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--                                 xtime_8(mc(0)) xor xtime_4(mc(0)) xor mc(0);
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--   inv_mix_col (15 downto 08) <= 
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--                                 xtime_8(mc(3)) xor xtime_4(mc(3)) xor mc(3) xor
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--                                 xtime_8(mc(2)) xor mc(2) xor
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--                                 xtime_8(mc(1)) xor xtime_4(mc(1)) xor xtime_2(mc(1)) xor 
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--                                 xtime_8(mc(0)) xor xtime_2(mc(0)) xor mc(0);
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--   inv_mix_col (07 downto 00) <= 
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--                                 xtime_8(mc(3)) xor xtime_2(mc(3)) xor mc(3) xor
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--                                 xtime_8(mc(2)) xor xtime_4(mc(2)) xor mc(2) xor
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--                                 xtime_8(mc(1)) xor mc(1) xor
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--                                 xtime_8(mc(0)) xor xtime_4(mc(0)) xor xtime_2(mc(0));
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end data_flow;

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