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[/] [minimips/] [trunk/] [miniMIPS/] [src/] [banc.vhd] - Blame information for rev 14

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------------------------------------------------------------------------------------
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--                                                                                --
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--    Copyright (c) 2004, Hangouet Samuel                                         --
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--                  , Jan Sebastien                                               --
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--                  , Mouton Louis-Marie                                          --
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--                  , Schneider Olivier     all rights reserved                   --
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--                                                                                --
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--    This file is part of miniMIPS.                                              --
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--                                                                                --
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--    miniMIPS is free software; you can redistribute it and/or modify            --
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--    it under the terms of the GNU Lesser General Public License as published by --
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--    the Free Software Foundation; either version 2.1 of the License, or         --
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--    (at your option) any later version.                                         --
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--                                                                                --
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--    miniMIPS is distributed in the hope that it will be useful,                 --
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--    but WITHOUT ANY WARRANTY; without even the implied warranty of              --
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--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the               --
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--    GNU Lesser General Public License for more details.                         --
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--                                                                                --
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--    You should have received a copy of the GNU Lesser General Public License    --
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--    along with miniMIPS; if not, write to the Free Software                     --
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--    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA   --
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--                                                                                --
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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--   lmouton@enserg.fr
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--   oschneid@enserg.fr
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--   shangoue@enserg.fr
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--
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--------------------------------------------------------------------------
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--                                                                      --
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--                                                                      --
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--               miniMIPS Processor : Register bank                     --
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--                                                                      --
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--                                                                      --
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--                                                                      --
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-- Authors : Hangouet  Samuel                                           --
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--           Jan       Sébastien                                        --
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--           Mouton    Louis-Marie                                      --
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--           Schneider Olivier                                          --
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--                                                                      --
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--                                                          june 2003   --
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--------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.pack_mips.all;
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entity banc is
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port (
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       clock : in bus1;
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       reset : in bus1;
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       -- Register addresses to read
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       reg_src1 : in bus5;
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       reg_src2 : in bus5;
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       -- Register address to write and its data
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       reg_dest : in bus5;
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       donnee   : in bus32;
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       -- Write signal
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       cmd_ecr  : in bus1;
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       -- Bank outputs
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       data_src1 : out bus32;
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       data_src2 : out bus32
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     );
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end banc;
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architecture rtl of banc is
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    -- The register bank
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    type tab_reg is array (1 to 31) of bus32;
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    signal registres : tab_reg;
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    signal adr_src1 : integer range 0 to 31;
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    signal adr_src2 : integer range 0 to 31;
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    signal adr_dest : integer range 0 to 31;
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begin
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    adr_src1 <= to_integer(unsigned(reg_src1));
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    adr_src2 <= to_integer(unsigned(reg_src2));
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    adr_dest <= to_integer(unsigned(reg_dest));
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    data_src1 <= (others => '0') when adr_src1=0 else
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                 registres(adr_src1);
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    data_src2 <= (others => '0') when adr_src2=0 else
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                 registres(adr_src2);
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    process(clock)
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    begin
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        if clock = '1' and clock'event then
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            if reset='1' then
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                for i in 1 to 31 loop
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                    registres(i) <= (others => '0');
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                end loop;
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            elsif cmd_ecr = '1' and adr_dest /= 0 then
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            -- The data is saved
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                registres(adr_dest) <= donnee;
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            end if;
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        end if;
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    end process;
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end rtl;

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