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mcafruni |
------------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- , Jan Sebastien --
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-- , Mouton Louis-Marie --
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-- , Schneider Olivier all rights reserved --
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-- --
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-- This file is part of miniMIPS. --
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-- --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation; either version 2 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with miniMIPS; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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-- lmouton@enserg.fr
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-- oschneid@enserg.fr
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-- shangoue@enserg.fr
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--
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--------------------------------------------------------------------------
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-- --
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-- --
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-- Processor miniMIPS : Memory access stage --
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-- --
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-- --
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-- --
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-- Authors : Hangouet Samuel --
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-- Jan Sébastien --
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-- Mouton Louis-Marie --
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-- Schneider Olivier --
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-- --
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-- june 2003 --
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.pack_mips.all;
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entity pps_mem is
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port
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(
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clock : in std_logic;
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clock2 : in std_logic;
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reset : in std_logic;
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stop_all : in std_logic; -- Unconditionnal locking of the outputs
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stop_all2 : in std_logic;
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clear : in std_logic; -- Clear the pipeline stage
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-- Interface with the control bus
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MTC_data : out bus32; -- Data to write in memory
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MTC_adr : out bus32; -- Address for memory
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MTC_r_w : out std_logic; -- Read/Write in memory
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MTC_req : out std_logic; -- Request access to memory
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CTM_data : in bus32; -- Data from memory
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-- Datas from Execution stage
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EX_adr : in bus32; -- Instruction address
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EX_data_ual : in bus32; -- Result of alu operation
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EX_adresse : in bus32; -- Result of the calculation of the address
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EX_adresse_p1p2 : in bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 2
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-- *** nao tinha essa entrada no original, so tinha a saida no EX ***
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EX_bra_confirm : in bus1; -- Confirmacao do branch no pipe 1 (26-07-18)
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-- ******************
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EX_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
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EX_ecr_reg : in std_logic; -- Effective writing of the result
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EX_op_mem : in std_logic; -- Memory operation needed
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EX_r_w : in std_logic; -- Type of memory operation (read or write)
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EX_exc_cause : in bus32; -- Potential exception cause
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EX_level : in level_type; -- Availability stage for the result for bypassing (Estágio de disponibilidade para o resultado de bypassing)
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EX_it_ok : in std_logic; -- Allow hardware interruptions
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-- Synchronous outputs for bypass unit
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MEM_adr : out bus32; -- Instruction address
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MEM_adr_reg_dest : out adr_reg_type; -- Destination register address
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MEM_ecr_reg : out std_logic; -- Writing of the destination register
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MEM_data_ecr : out bus32; -- Data to write (from alu or memory)
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MEM_exc_cause : out bus32; -- Potential exception cause
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MEM_level : out level_type; -- Availability stage for the result for bypassing (Estágio de disponibilidade para o resultado de bypassing)
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MEM_it_ok : out std_logic; -- Allow hardware interruptions
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--modificação
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-- Interface with the control bus
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MTC_data2 : out bus32; -- Data to write in memory
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MTC_adr2 : out bus32; -- Address for memory
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MTC_r_w2 : out std_logic; -- Read/Write in memory
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MTC_req2 : out std_logic; -- Request access to memory
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CTM_data2 : in bus32; -- Data from memory
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-- Datas from Execution 2 stage
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EX_adr2 : in bus32; -- Instruction address
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EX_data_ual2 : in bus32; -- Result of alu operation
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EX_adresse2 : in bus32; -- Result of the calculation of the address
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EX_adresse_p2p1 : in bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 1
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-- *** nao tinha essa entrada no original, so tinha a saida no EX2 ***
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EX_bra_confirm2 : in bus1; -- Confirmacao do branch no pipe 2 (26-07-18)
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-- ******************
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EX_adr_reg_dest2 : in adr_reg_type; -- Destination register address for the result
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EX_ecr_reg2 : in std_logic; -- Effective writing of the result
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EX_op_mem2 : in std_logic; -- Memory operation needed
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EX_r_w2 : in std_logic; -- Type of memory operation (read or write)
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EX_exc_cause2 : in bus32; -- Potential exception cause
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EX_level2 : in level_type; -- Availability stage for the result for bypassing (Estágio de disponibilidade para o resultado de bypassing)
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EX_it_ok2 : in std_logic; -- Allow hardware interruptions
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-- Synchronous outputs for bypass unit
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MEM_adr2 : out bus32; -- Instruction address
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MEM_adr_reg_dest2 : out adr_reg_type; -- Destination register address
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MEM_ecr_reg2 : out std_logic; -- Writing of the destination register
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MEM_data_ecr2 : out bus32; -- Data to write (from alu or memory)
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MEM_exc_cause2 : out bus32; -- Potential exception cause
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MEM_level2 : out level_type; -- Availability stage for the result for bypassing(Estágio de disponibilidade para o resultado de bypassing)
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MEM_it_ok2 : out std_logic -- Allow hardware interruptions
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);
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end pps_mem;
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architecture rtl of pps_mem is
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signal tmp_data_ecr : bus32; -- Selection of the data source (memory or alu)
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signal tmp_data_ecr2 : bus32; -- Selection of the data source (memory or alu)
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signal sel_MTC : bus2;
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begin
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sel_MTC <= EX_bra_confirm & EX_bra_confirm2;
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with sel_MTC select
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MTC_adr <= EX_adresse_p2p1 when "01",
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EX_adresse when others;
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-- with sel_MTC select
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-- MTC_r_w <= EX_r_w2 when "01",
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-- EX_r_w when others;
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--
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-- with sel_MTC select
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-- MTC_req <= EX_op_mem2 and not clear when "01",
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-- EX_op_mem and not clear when others;
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--
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-- with sel_MTC select
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-- MTC_data <= EX_data_ual2 when "01",
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-- EX_data_ual when others;
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with sel_MTC select
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MTC_adr2 <= EX_adresse_p1p2 when "10",
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EX_adresse2 when others;
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-- with sel_MTC select
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-- MTC_r_w2 <= EX_r_w when "10",
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-- EX_r_w2 when others;
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--
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-- with sel_MTC select
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-- MTC_req2 <= EX_op_mem and not clear when "10",
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-- EX_op_mem2 and not clear when others;
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--
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-- with sel_MTC select
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-- MTC_data2 <= EX_data_ual when "10",
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-- EX_data_ual2 when others;
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-- Bus controler connexions
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-- MTC_adr <= EX_adresse; -- Connexion of the address
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MTC_r_w <= EX_r_w; -- Connexion of R/W
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MTC_data <= EX_data_ual; -- Connexion of the data bus
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MTC_req <= EX_op_mem and not clear; -- Connexion of the request (if there is no clearing of the pipeline)
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-- Bus controler connexions 2nd pipe
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-- MTC_adr2 <= EX_adresse2; -- Connexion of the address
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MTC_r_w2 <= EX_r_w2; -- Connexion of R/W
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MTC_data2 <= EX_data_ual2; -- Connexion of the data bus
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MTC_req2 <= EX_op_mem2 and not clear; -- Connexion of the request (if there is no clearing of the pipeline)
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-- Preselection of the data source for the outputs
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tmp_data_ecr <= CTM_data when EX_op_mem = '1' else EX_data_ual;
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tmp_data_ecr2 <= CTM_data2 when EX_op_mem2 = '1' else EX_data_ual2; --(modificação) para EX2
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-- Set the synchronous outputs
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process (clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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MEM_adr <= (others => '0');
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MEM_adr_reg_dest <= (others => '0');
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MEM_ecr_reg <= '0';
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MEM_data_ecr <= (others => '0');
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MEM_exc_cause <= IT_NOEXC;
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MEM_level <= LVL_DI;
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MEM_it_ok <= '0';
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elsif stop_all = '0' then
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if clear = '1' then -- Clear the stage
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MEM_adr <= EX_adr;
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MEM_adr_reg_dest <= (others => '0');
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MEM_ecr_reg <= '0';
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MEM_data_ecr <= (others => '0');
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MEM_exc_cause <= IT_NOEXC;
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MEM_level <= LVL_DI;
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MEM_it_ok <= '0';
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else -- Normal evolution
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MEM_adr <= EX_adr;
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MEM_adr_reg_dest <= EX_adr_reg_dest;
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MEM_ecr_reg <= EX_ecr_reg;
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MEM_data_ecr <= tmp_data_ecr;
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MEM_exc_cause <= EX_exc_cause;
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MEM_level <= EX_level;
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MEM_it_ok <= EX_it_ok;
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end if;
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end if;
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end if;
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end process;
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process (clock2)
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begin
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if rising_edge(clock2) then
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if reset = '1' then
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MEM_adr2 <= (others => '0');
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MEM_adr_reg_dest2 <= (others => '0');
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MEM_ecr_reg2 <= '0';
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MEM_data_ecr2 <= (others => '0');
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MEM_exc_cause2 <= IT_NOEXC;
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MEM_level2 <= LVL_DI;
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MEM_it_ok2 <= '0';
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elsif stop_all2 = '0' then
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if clear = '1' then -- Clear the stage
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MEM_adr2 <= EX_adr2;
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MEM_adr_reg_dest2 <= (others => '0');
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MEM_ecr_reg2 <= '0';
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MEM_data_ecr2 <= (others => '0');
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MEM_exc_cause2 <= IT_NOEXC;
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MEM_level2 <= LVL_DI;
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MEM_it_ok2 <= '0';
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else -- Normal evolution
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MEM_adr2 <= EX_adr2;
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MEM_adr_reg_dest2 <= EX_adr_reg_dest2;
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MEM_ecr_reg2 <= EX_ecr_reg2;
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MEM_data_ecr2 <= tmp_data_ecr2;
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MEM_exc_cause2 <= EX_exc_cause2;
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MEM_level2 <= EX_level2;
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MEM_it_ok2 <= EX_it_ok2;
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end if;
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end if;
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end if;
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end process;
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end rtl;
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