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[/] [minimips_superscalar/] [trunk/] [bench/] [rom.vhd] - Blame information for rev 10

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1 3 mcafruni
-------------------------------------------------------------------------------
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--                                                                           --
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--                                                                           --
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-- miniMIPS Superscalar Processor : testbench                                --
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-- based on miniMIPS Processor                                               --
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--                                                                           --
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--                                                                           --
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-- Author : Miguel Cafruni                                                   --
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-- miguel_cafruni@hotmail.com                                                --
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--                                                           December 2018   --
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-------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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--
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--   lmouton@enserg.fr  (2003 version)
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--   oschneid@enserg.fr (2003 version)
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--   shangoue@enserg.fr (2003 version)
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--   miguel_cafruni@hotmail.com (Superscalar version 2018)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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library work;
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use work.pack_mips.all;
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entity rom is
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   generic (mem_size : natural := 256; -- Size of the memory in words
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            start : natural := 32768;
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            latency : time := 0 ns);
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   port(
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       adr : in bus32;
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       donnee : out bus32;
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       ack : out std_logic;
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       adr2 : in bus32;
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       donnee2 : out bus32;
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       ack2 : out std_logic;
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       load : in std_logic;
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       fname : in string
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   );
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end;
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architecture bench of rom is
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    type storage_array is array(natural range start to start+4*mem_size - 1) of bus8;
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    signal storage : storage_array := (others => (others => '0'));    -- The memory
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    signal adresse : bus16;
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    signal taille : bus16;
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begin
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    process (load)
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        -- Variables for loading the memory
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        -- The reading is done by blocks
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        type bin is file of integer;                    -- Binary type file
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        file load_file : bin;
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        variable c : integer ;                          -- Integer (32 bits) read in the file
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        variable index : integer range storage'range;   -- Index for loading
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        variable word : bus32;                          -- Word read in the file
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        variable taille_bloc : integer;                 -- Current size of the block to load
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        variable tmp : bus16;
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        variable status : file_open_status;
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        variable s : line;
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        variable big_endian : boolean := true;          -- Define if the processor (on which we work) is little or big endian
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    begin
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    if load='1' then
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        -- Reading of the file de fill the memory at the defined address
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        file_open(status, load_file, fname, read_mode);
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        if status=open_ok then
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            while not endfile(load_file) loop
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                -- Read the header of the block
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                read(load_file, c);                             -- Read a 32 bit long word
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                word := bus32(to_unsigned(c, 32));              -- Conversion to a bit vector
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                if big_endian then
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                    tmp := word(7 downto 0) & word(15 downto 8);
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                else
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                    tmp := word(31 downto 16);
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                end if;
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                index := to_integer(unsigned(tmp));
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                adresse <= tmp;
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                if big_endian then
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                    tmp := word(23 downto 16) & word(31 downto 24);
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                else
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                    tmp := word(15 downto 0);
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                end if;
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                taille_bloc := to_integer(unsigned(tmp)) / 4;
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                taille <= tmp;
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                -- Load the block in the ROM
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                for n in 1 to taille_bloc loop
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                    -- The header file is not correct (block too small, ROM to small ...)
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                    -- The simulation is stopped
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                    assert (not endfile(load_file) and (index<=storage'high))
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                        report "L'image n'a pas le bon format ou ne rentre pas dans la rom."
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                        severity error;
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                    if not endfile(load_file) and (index<=storage'high) then
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                        read(load_file, c);
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                        word := bus32(to_unsigned(c, 32));
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                        if (c < 0) then
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                          word := not(word);
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                          word := std_logic_vector(unsigned(word)+1);
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                        end if;
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                        for i in 0 to 3 loop
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                            if big_endian then
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                                storage(index+i) <= word(8*(i+1)-1 downto 8*i);
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                            else
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                                storage(index+(3-i)) <= word(8*(i+1)-1 downto 8*i);
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                            end if;
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                        end loop;
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                        index := index + 4;
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                    end if;
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                end loop;
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            end loop;
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            file_close(load_file);
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        else
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            assert false
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                report "Impossible d'ouvrir le fichier specifie."
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                severity error;
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        end if;
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    end if;
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    end process;
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    process(adr) -- Request for reading the ROM
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        variable inadr : integer;
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        variable i : natural;
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    begin
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            inadr := to_integer(unsigned(adr));
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            if (inadr>=storage'low) and (inadr<=storage'high) then
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                for i in 0 to 3 loop
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                    donnee(8*(i+1)-1 downto 8*i) <= storage(inadr+3-i) after latency;
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                end loop;
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                ack <= '0', '1' after latency;
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            else
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                donnee <= (others => 'Z');
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                ack <= 'L';
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            end if;
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    end process;
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    process(adr2) -- Request for reading the ROM
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        variable inadr2 : integer;
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        variable i2 : natural;
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    begin
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            inadr2 := to_integer(unsigned(adr2));
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            if (inadr2>=storage'low) and (inadr2<=storage'high) then
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                for i2 in 0 to 3 loop
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                    donnee2(8*(i2+1)-1 downto 8*i2) <= storage(inadr2+3-i2) after latency;
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                end loop;
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                ack2 <= '0', '1' after latency;
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            else
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                donnee2 <= (others => 'Z');
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                ack2 <= 'L';
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            end if;
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    end process;
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end bench;
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