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mcafruni |
-------------------------------------------------------------------------------
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-- --
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-- --
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-- miniMIPS Superscalar Processor : Enumerations and components declarations --
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-- based on miniMIPS Processor --
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-- --
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-- --
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-- Author : Miguel Cafruni --
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-- miguel_cafruni@hotmail.com --
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-- December 2018 --
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package pack_mips is
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-- Type signal on n bits
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subtype bus64 is std_logic_vector(63 downto 0);
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subtype bus33 is std_logic_vector(32 downto 0);
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subtype bus32 is std_logic_vector(31 downto 0);
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subtype bus31 is std_logic_vector(30 downto 0);
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subtype bus26 is std_logic_vector(25 downto 0);
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subtype bus24 is std_logic_vector(23 downto 0);
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subtype bus16 is std_logic_vector(15 downto 0);
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subtype bus8 is std_logic_vector(7 downto 0);
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subtype bus7 is std_logic_vector(6 downto 0);
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subtype bus6 is std_logic_vector(5 downto 0);
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subtype bus5 is std_logic_vector(4 downto 0);
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subtype bus4 is std_logic_vector(3 downto 0);
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subtype bus2 is std_logic_vector(1 downto 0);
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subtype bus1 is std_logic;
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-- Address of a register type
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subtype adr_reg_type is std_logic_vector(5 downto 0);
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-- Coding of the level of data availability for UR
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subtype level_type is std_logic_vector(2 downto 0);
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constant LVL_DI2 : level_type := "110"; -- Data available from the op2 of DI2 stage
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constant LVL_EX2 : level_type := "101"; -- Data available from the data_ual register of EX2 stage
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constant LVL_MEM2 : level_type := "100"; -- Data available from the data_ecr register of MEM2 stage
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constant LVL_DI : level_type := "011"; -- Data available from the op2 of DI stage
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constant LVL_EX : level_type := "010"; -- Data available from the data_ual register of EX stage
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constant LVL_MEM : level_type := "001"; -- Data available from the data_ecr register of MEM stage
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constant LVL_REG : level_type := "000"; -- Data available only in the register bank
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-- Different values of cause exceptions
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constant IT_NOEXC : bus32 := X"00000000";
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constant IT_ITMAT : bus32 := X"00000001";
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constant IT_OVERF : bus32 := X"00000002";
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constant IT_ERINS : bus32 := X"00000004";
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constant IT_BREAK : bus32 := X"00000008";
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constant IT_SCALL : bus32 := X"00000010";
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-- Operation type of the coprocessor system (only the low 16 bits are valid)
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constant SYS_NOP : bus32 := X"0000_0000";
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constant SYS_MASK : bus32 := X"0000_0001";
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constant SYS_UNMASK : bus32 := X"0000_0002";
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constant SYS_ITRET : bus32 := X"0000_0004";
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-- Type for the alu control
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subtype alu_ctrl_type is std_logic_vector(27 downto 0);
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-- Arithmetical operations
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constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign‰
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constant OP_ADDU : alu_ctrl_type := "0100000000000000000000000000"; -- op1 + op2 non sign‰
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constant OP_SUB : alu_ctrl_type := "0010000000000000000000000000"; -- op1 - op2 sign‰
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constant OP_SUBU : alu_ctrl_type := "0001000000000000000000000000"; -- op1 - op2 non sign‰e
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-- Logical operations
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constant OP_AND : alu_ctrl_type := "0000100000000000000000000000"; -- et logique
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constant OP_OR : alu_ctrl_type := "0000010000000000000000000000"; -- ou logique
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constant OP_XOR : alu_ctrl_type := "0000001000000000000000000000"; -- ou exclusif logique
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constant OP_NOR : alu_ctrl_type := "0000000100000000000000000000"; -- non ou logique
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-- Tests : result to one if ok
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constant OP_SLT : alu_ctrl_type := "0000000010000000000000000000"; -- op1 < op2 (sign‰)
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constant OP_SLTU : alu_ctrl_type := "0000000001000000000000000000"; -- op1 < op2 (non sign‰)
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constant OP_EQU : alu_ctrl_type := "0000000000100000000000000000"; -- op1 = op2
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constant OP_NEQU : alu_ctrl_type := "0000000000010000000000000000"; -- op1 /= op2
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constant OP_SNEG : alu_ctrl_type := "0000000000001000000000000000"; -- op1 < 0
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constant OP_SPOS : alu_ctrl_type := "0000000000000100000000000000"; -- op1 > 0
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constant OP_LNEG : alu_ctrl_type := "0000000000000010000000000000"; -- op1 <= 0
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constant OP_LPOS : alu_ctrl_type := "0000000000000001000000000000"; -- op1 >= 0
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-- Multiplications
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constant OP_MULT : alu_ctrl_type := "0000000000000000100000000000"; -- op1 * op2 sign‰ (chargement des poids faibles)
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constant OP_MULT2 : alu_ctrl_type := "0000000000000000000000000000"; -- op1 * op2 sign - MULT2 25.05.18 - Miguel
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constant OP_MULTU : alu_ctrl_type := "0000000000000000010000000000"; -- op1 * op2 non sign‰ (chargement des poids faibles)
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-- Shifts
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constant OP_SLL : alu_ctrl_type := "0000000000000000001000000000"; -- decallage logique a gauche
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constant OP_SRL : alu_ctrl_type := "0000000000000000000100000000"; -- decallage logique a droite
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constant OP_SRA : alu_ctrl_type := "0000000000000000000010000000"; -- decallage arithmetique a droite
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constant OP_LUI : alu_ctrl_type := "0000000000000000000001000000"; -- met en poids fort la valeur immediate
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-- Access to internal registers
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constant OP_MFHI : alu_ctrl_type := "0000000000000000000000100000"; -- lecture des poids forts
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constant OP_MFLO : alu_ctrl_type := "0000000000000000000000010000"; -- lecture des poids faibles
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constant OP_MTHI : alu_ctrl_type := "0000000000000000000000001000"; -- ecriture des poids forts
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constant OP_MTLO : alu_ctrl_type := "0000000000000000000000000100"; -- ecriture des poids faibles
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-- Operations which do nothing but are useful
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constant OP_OUI : alu_ctrl_type := "0000000000000000000000000010"; -- met a 1 le bit de poids faible en sortie
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constant OP_OP2 : alu_ctrl_type := "0000000000000000000000000001"; -- recopie l'operande 2 en sortie
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-- Starting boot address (after reset)
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constant ADR_INIT : bus32 := X"00000000";
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constant ADR_INIT4 : bus32 := X"00000004";
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constant INS_NOP : bus32 := X"00000000";
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constant zero : bus1 := '0';
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-- Internal component of the pipeline stage
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component alu
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port (
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clock : in bus1;
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reset : in bus1;
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op1 : in bus32;
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op2 : in bus32;
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ctrl : in alu_ctrl_type;
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hilo_p2 : in bus64;
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hilo_p1p2 : out bus64;
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res : out bus32;
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overflow : out bus1
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);
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end component;
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component alu2
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port (
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clock : in bus1;
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reset : in bus1;
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op1 : in bus32;
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op2 : in bus32;
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ctrl : in alu_ctrl_type;
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hilo_p1 : in bus64;
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hilo_p2p1 : out bus64;
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res : out bus32;
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overflow : out bus1
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);
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end component;
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-- Pipeline stage components
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component pps_pf
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port (
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clock : in bus1;
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clock2 : in bus1;
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reset : in bus1;
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stop_all : in bus1;
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stop_all2: in bus1;
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bra_cmd : in bus1;
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bra_adr : in bus32;
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exch_cmd : in bus1;
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exch_adr : in bus32;
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bra_cmd2 : in bus1;
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bra_adr2 : in bus32;
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exch_cmd2 : in bus1;
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exch_adr2 : in bus32;
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stop_pf : in bus1;
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stop_pf2 : in bus1;
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PF_pc : out bus32;
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PF_pc_4 : out bus32
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);
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end component;
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component clock_gate
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port (
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clock_in1 : in bus1;
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clock_in2 : in bus1;
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clock_out1 : out bus1;
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clock_out2 : out bus1;
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gate1 : in bus1;
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gate2 : in bus1
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);
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end component;
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component delay_gate
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port (
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clock : in bus1;
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in1 : in bus1;
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in2 : in bus1;
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in3 : in bus1;
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in4 : in bus1;
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in5 : in bus1;
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in6 : in bus1;
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in7 : in bus1;
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in8 : in bus1;
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in9 : in bus1;
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in10 : in bus1;
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in11 : in bus1;
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in12 : in bus1;
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out1 : out bus1;
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out2 : out bus1;
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out3 : out bus1;
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out4 : out bus1;
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out5 : out bus1;
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out6 : out bus1;
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out7 : out bus1;
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out8 : out bus1;
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out9 : out bus1;
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out10 : out bus1;
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out11 : out bus1;
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out12 : out bus1
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);
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end component;
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component pps_ei
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port (
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clock : in bus1;
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reset : in bus1;
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clear : in bus1;
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stop_all : in bus1;
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stop_ei : in bus1;
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genop : in bus1;
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CTE_instr : in bus32;
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ETC_adr : out bus32;
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PF_pc : in bus32;
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EI_instr : out bus32;
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EI_adr : out bus32;
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EI_it_ok : out bus1
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);
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end component;
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component pps_ei_2
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port (
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clock : in bus1;
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reset : in bus1;
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clear : in bus1;
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stop_all2 : in bus1;
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stop_ei : in bus1;
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genop : in bus1;
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CTE_instr : in bus32;
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ETC_adr : out bus32;
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PF_pc : in bus32;
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EI_instr : out bus32;
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EI_adr : out bus32;
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EI_it_ok : out bus1
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);
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end component;
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component pps_di
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port (
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clock : in bus1;
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reset : in bus1;
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stop_all : in bus1;
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clear : in bus1;
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bra_detect : out bus1;
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adr_reg1 : out adr_reg_type;
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adr_reg2 : out adr_reg_type;
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use1 : out bus1;
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use2 : out bus1;
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--iload : out bus1;
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istore : out bus1;
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stop_di : in bus1;
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data1 : in bus32;
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data2 : in bus32;
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EI_adr : in bus32;
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EI_instr : in bus32;
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EI_it_ok : in bus1;
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DI_bra : out bus1;
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DI_link : out bus1;
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DI_op1 : out bus32;
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DI_op2 : out bus32;
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DI_code_ual : out alu_ctrl_type;
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DI_offset : out bus32;
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DI_adr_reg_dest : out adr_reg_type;
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DI_ecr_reg : out bus1;
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DI_mode : out bus1;
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DI_op_mem : out bus1;
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DI_r_w : out bus1;
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DI_adr : out bus32;
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DI_exc_cause : out bus32;
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DI_level : out level_type;
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DI_it_ok : out bus1
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--DI_SRC1 : out adr_reg_type;
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--DI_SRC2 : out adr_reg_type
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);
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end component;
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component pps_di_2
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port (
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clock : in bus1;
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reset : in bus1;
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stop_all2 : in bus1;
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clear : in bus1;
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bra_detect : out bus1;
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adr_reg1 : out adr_reg_type;
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adr_reg2 : out adr_reg_type;
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use1 : out bus1;
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use2 : out bus1;
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--iload2 : out bus1;
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istore2 : out bus1;
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stop_di : in bus1;
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data1 : in bus32;
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data2 : in bus32;
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EI_adr : in bus32;
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EI_instr : in bus32;
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EI_it_ok : in bus1;
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DI_bra : out bus1;
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DI_link : out bus1;
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DI_op1 : out bus32;
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DI_op2 : out bus32;
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DI_code_ual : out alu_ctrl_type;
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DI_offset : out bus32;
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DI_adr_reg_dest : out adr_reg_type;
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DI_ecr_reg : out bus1;
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DI_mode : out bus1;
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DI_op_mem : out bus1;
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DI_r_w : out bus1;
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DI_adr : out bus32;
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|
|
DI_exc_cause : out bus32;
|
| 330 |
|
|
DI_level : out level_type;
|
| 331 |
|
|
DI_it_ok : out bus1
|
| 332 |
|
|
--DI2_SRC3 : out adr_reg_type;
|
| 333 |
|
|
--DI2_SRC4 : out adr_reg_type
|
| 334 |
|
|
);
|
| 335 |
|
|
end component;
|
| 336 |
|
|
|
| 337 |
|
|
component pps_ex
|
| 338 |
|
|
port (
|
| 339 |
|
|
clock : in bus1;
|
| 340 |
|
|
clock2 : in bus1;
|
| 341 |
|
|
reset : in bus1;
|
| 342 |
|
|
stop_all : in bus1;
|
| 343 |
|
|
stop_all2 : in bus1;
|
| 344 |
|
|
clear : in bus1;
|
| 345 |
|
|
|
| 346 |
|
|
DI_bra : in bus1;
|
| 347 |
|
|
DI_link : in bus1;
|
| 348 |
|
|
DI_op1 : in bus32;
|
| 349 |
|
|
DI_op2 : in bus32;
|
| 350 |
|
|
DI_code_ual : in alu_ctrl_type;
|
| 351 |
|
|
DI_offset : in bus32;
|
| 352 |
|
|
DI_adr_reg_dest : in adr_reg_type;
|
| 353 |
|
|
DI_ecr_reg : in bus1;
|
| 354 |
|
|
DI_mode : in bus1;
|
| 355 |
|
|
DI_op_mem : in bus1;
|
| 356 |
|
|
DI_r_w : in bus1;
|
| 357 |
|
|
DI_adr : in bus32;
|
| 358 |
|
|
DI_exc_cause : in bus32;
|
| 359 |
|
|
DI_level : in level_type;
|
| 360 |
|
|
DI_it_ok : in bus1;
|
| 361 |
|
|
EX2_data_hilo : in bus64;
|
| 362 |
|
|
EX_data_hilo : out bus64;
|
| 363 |
|
|
EX_adr : out bus32;
|
| 364 |
|
|
EX_bra_confirm : out bus1;
|
| 365 |
|
|
EX_data_ual : out bus32;
|
| 366 |
|
|
EX_adresse : out bus32;
|
| 367 |
|
|
EX_adresse_p1p2 : out bus32;
|
| 368 |
|
|
EX_adr_reg_dest : out adr_reg_type;
|
| 369 |
|
|
EX_ecr_reg : out bus1;
|
| 370 |
|
|
EX_op_mem : out bus1;
|
| 371 |
|
|
EX_r_w : out bus1;
|
| 372 |
|
|
EX_exc_cause : out bus32;
|
| 373 |
|
|
EX_level : out level_type;
|
| 374 |
|
|
EX_it_ok : out bus1
|
| 375 |
|
|
-- EX_SRC1 : out adr_reg_type;
|
| 376 |
|
|
-- EX_SRC2 : out adr_reg_type
|
| 377 |
|
|
|
| 378 |
|
|
);
|
| 379 |
|
|
end component;
|
| 380 |
|
|
|
| 381 |
|
|
component pps_ex_2
|
| 382 |
|
|
port(
|
| 383 |
|
|
clock : in bus1;
|
| 384 |
|
|
clock2 : in bus1;
|
| 385 |
|
|
reset : in bus1;
|
| 386 |
|
|
stop_all : in bus1;
|
| 387 |
|
|
stop_all2 : in bus1; -- Unconditionnal locking of outputs
|
| 388 |
|
|
clear : in bus1; -- Clear the pipeline stage
|
| 389 |
|
|
|
| 390 |
|
|
-- Datas from DI stage
|
| 391 |
|
|
DI_bra : in bus1; -- Branch instruction
|
| 392 |
|
|
DI_link : in bus1; -- Branch with link
|
| 393 |
|
|
DI_op1 : in bus32; -- Operand 1 for alu
|
| 394 |
|
|
DI_op2 : in bus32; -- Operand 2 for alu
|
| 395 |
|
|
DI_code_ual : in alu_ctrl_type; -- Alu operation
|
| 396 |
|
|
DI_offset : in bus32; -- Offset for address calculation
|
| 397 |
|
|
DI_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
|
| 398 |
|
|
DI_ecr_reg : in bus1; -- Effective writing of the result
|
| 399 |
|
|
DI_mode : in bus1; -- Address mode (relative to pc ou index by a register)
|
| 400 |
|
|
DI_op_mem : in bus1; -- Memory operation
|
| 401 |
|
|
DI_r_w : in bus1; -- Type of memory operation (read or write)
|
| 402 |
|
|
DI_adr : in bus32; -- Instruction address
|
| 403 |
|
|
DI_exc_cause : in bus32; -- Potential cause exception
|
| 404 |
|
|
DI_level : in level_type; -- Availability stage of the result for bypassing
|
| 405 |
|
|
DI_it_ok : in bus1; -- Allow hardware interruptions
|
| 406 |
|
|
|
| 407 |
|
|
EX_data_hilo : in bus64;--resultado da multiplicacao do pieline 1
|
| 408 |
|
|
EX2_data_hilo : out bus64;
|
| 409 |
|
|
-- Synchronous outputs to MEM stage
|
| 410 |
|
|
EX_adr : out bus32; -- Instruction address
|
| 411 |
|
|
EX_bra_confirm : out bus1; -- Branch execution confirmation
|
| 412 |
|
|
EX_data_ual : out bus32; -- Ual result
|
| 413 |
|
|
EX_adresse : out bus32; -- Address calculation result
|
| 414 |
|
|
EX_adresse_p2p1 : out bus32;-- 12-08-2018
|
| 415 |
|
|
EX_adr_reg_dest : out adr_reg_type; -- Destination register for the result
|
| 416 |
|
|
EX_ecr_reg : out bus1; -- Effective writing of the result
|
| 417 |
|
|
EX_op_mem : out bus1; -- Memory operation needed
|
| 418 |
|
|
EX_r_w : out bus1; -- Type of memory operation (read or write)
|
| 419 |
|
|
EX_exc_cause : out bus32; -- Potential cause exception
|
| 420 |
|
|
EX_level : out level_type; -- Availability stage of result for bypassing
|
| 421 |
|
|
EX_it_ok : out bus1 -- Allow hardware interruptions
|
| 422 |
|
|
);
|
| 423 |
|
|
end component;
|
| 424 |
|
|
|
| 425 |
|
|
component pps_mem
|
| 426 |
|
|
port (
|
| 427 |
|
|
clock : in bus1;
|
| 428 |
|
|
clock2 : in bus1;
|
| 429 |
|
|
reset : in bus1;
|
| 430 |
|
|
stop_all : in bus1;
|
| 431 |
|
|
stop_all2 : in bus1;
|
| 432 |
|
|
|
| 433 |
|
|
clear : in bus1;
|
| 434 |
|
|
|
| 435 |
|
|
MTC_data : out bus32;
|
| 436 |
|
|
MTC_adr : out bus32;
|
| 437 |
|
|
MTC_r_w : out bus1;
|
| 438 |
|
|
MTC_req : out bus1;
|
| 439 |
|
|
CTM_data : in bus32;
|
| 440 |
|
|
|
| 441 |
|
|
EX_adr : in bus32;
|
| 442 |
|
|
EX_data_ual : in bus32;
|
| 443 |
|
|
EX_adresse : in bus32;
|
| 444 |
|
|
EX_adresse_p1p2 : in bus32;-- 12-08-2018
|
| 445 |
|
|
EX_bra_confirm : in bus1;-- Confirmacao do branch no pipe 1 (26-07-18)
|
| 446 |
|
|
EX_adr_reg_dest : in adr_reg_type;
|
| 447 |
|
|
EX_ecr_reg : in bus1;
|
| 448 |
|
|
EX_op_mem : in bus1;
|
| 449 |
|
|
EX_r_w : in bus1;
|
| 450 |
|
|
EX_exc_cause : in bus32;
|
| 451 |
|
|
EX_level : in level_type;
|
| 452 |
|
|
EX_it_ok : in bus1;
|
| 453 |
|
|
|
| 454 |
|
|
MEM_adr : out bus32;
|
| 455 |
|
|
MEM_adr_reg_dest : out adr_reg_type;
|
| 456 |
|
|
MEM_ecr_reg : out bus1;
|
| 457 |
|
|
MEM_data_ecr : out bus32;
|
| 458 |
|
|
MEM_exc_cause : out bus32;
|
| 459 |
|
|
MEM_level : out level_type;
|
| 460 |
|
|
MEM_it_ok : out bus1;
|
| 461 |
|
|
|
| 462 |
|
|
-- duplicacao
|
| 463 |
|
|
MTC_data2 : out bus32;
|
| 464 |
|
|
MTC_adr2 : out bus32;
|
| 465 |
|
|
MTC_r_w2 : out bus1;
|
| 466 |
|
|
MTC_req2 : out bus1;
|
| 467 |
|
|
CTM_data2 : in bus32;
|
| 468 |
|
|
|
| 469 |
|
|
EX_adr2 : in bus32;
|
| 470 |
|
|
EX_data_ual2 : in bus32;
|
| 471 |
|
|
EX_adresse2 : in bus32;
|
| 472 |
|
|
EX_adresse_p2p1 : in bus32;-- 12-08-2018
|
| 473 |
|
|
EX_bra_confirm2 : in bus1;-- Confirmacao do branch no pipe 2 (26-07-18)
|
| 474 |
|
|
EX_adr_reg_dest2 : in adr_reg_type;
|
| 475 |
|
|
EX_ecr_reg2 : in bus1;
|
| 476 |
|
|
EX_op_mem2 : in bus1;
|
| 477 |
|
|
EX_r_w2 : in bus1;
|
| 478 |
|
|
EX_exc_cause2 : in bus32;
|
| 479 |
|
|
EX_level2 : in level_type;
|
| 480 |
|
|
EX_it_ok2 : in bus1;
|
| 481 |
|
|
|
| 482 |
|
|
MEM_adr2 : out bus32;
|
| 483 |
|
|
MEM_adr_reg_dest2 : out adr_reg_type;
|
| 484 |
|
|
MEM_ecr_reg2 : out bus1;
|
| 485 |
|
|
MEM_data_ecr2 : out bus32;
|
| 486 |
|
|
MEM_exc_cause2 : out bus32;
|
| 487 |
|
|
MEM_level2 : out level_type;
|
| 488 |
|
|
MEM_it_ok2 : out bus1
|
| 489 |
|
|
);
|
| 490 |
|
|
end component;
|
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
|
|
component renvoi
|
| 494 |
|
|
port (
|
| 495 |
|
|
adr1 : in adr_reg_type;
|
| 496 |
|
|
adr2 : in adr_reg_type;
|
| 497 |
|
|
use1 : in bus1;
|
| 498 |
|
|
use2 : in bus1;
|
| 499 |
|
|
|
| 500 |
|
|
data1 : out bus32;
|
| 501 |
|
|
data2 : out bus32;
|
| 502 |
|
|
alea : out bus1;
|
| 503 |
|
|
|
| 504 |
|
|
DI_level : in level_type;
|
| 505 |
|
|
DI_adr : in adr_reg_type;
|
| 506 |
|
|
DI_ecr : in bus1;
|
| 507 |
|
|
DI_data : in bus32;
|
| 508 |
|
|
|
| 509 |
|
|
EX_level : in level_type;
|
| 510 |
|
|
EX_adr : in adr_reg_type;
|
| 511 |
|
|
EX_ecr : in bus1;
|
| 512 |
|
|
EX_data : in bus32;
|
| 513 |
|
|
|
| 514 |
|
|
MEM_level : in level_type;
|
| 515 |
|
|
MEM_adr : in adr_reg_type;
|
| 516 |
|
|
MEM_ecr : in bus1;
|
| 517 |
|
|
MEM_data : in bus32;
|
| 518 |
|
|
|
| 519 |
|
|
interrupt : in bus1;
|
| 520 |
|
|
|
| 521 |
|
|
write_data : out bus32;
|
| 522 |
|
|
write_adr : out bus5;
|
| 523 |
|
|
write_GPR : out bus1;
|
| 524 |
|
|
write_SCP : out bus1;
|
| 525 |
|
|
|
| 526 |
|
|
read_adr1 : out bus5;
|
| 527 |
|
|
read_adr2 : out bus5;
|
| 528 |
|
|
read_data1_GPR : in bus32;
|
| 529 |
|
|
read_data1_SCP : in bus32;
|
| 530 |
|
|
read_data2_GPR : in bus32;
|
| 531 |
|
|
read_data2_SCP : in bus32;
|
| 532 |
|
|
|
| 533 |
|
|
--duplicacao
|
| 534 |
|
|
adr3 : in adr_reg_type;
|
| 535 |
|
|
adr4 : in adr_reg_type;
|
| 536 |
|
|
use12 : in bus1;
|
| 537 |
|
|
use22 : in bus1;
|
| 538 |
|
|
|
| 539 |
|
|
data3 : out bus32;
|
| 540 |
|
|
data4 : out bus32;
|
| 541 |
|
|
alea2 : out bus1;
|
| 542 |
|
|
|
| 543 |
|
|
DI_level2 : in level_type;
|
| 544 |
|
|
DI_adr2 : in adr_reg_type;
|
| 545 |
|
|
DI_ecr2 : in bus1;
|
| 546 |
|
|
DI_data2 : in bus32;
|
| 547 |
|
|
|
| 548 |
|
|
EX_level2 : in level_type;
|
| 549 |
|
|
EX_adr2 : in adr_reg_type;
|
| 550 |
|
|
EX_ecr2 : in bus1;
|
| 551 |
|
|
EX_data2 : in bus32;
|
| 552 |
|
|
|
| 553 |
|
|
MEM_level2 : in level_type;
|
| 554 |
|
|
MEM_adr2 : in adr_reg_type;
|
| 555 |
|
|
MEM_ecr2 : in bus1;
|
| 556 |
|
|
MEM_data2 : in bus32;
|
| 557 |
|
|
|
| 558 |
|
|
write_data2 : out bus32;
|
| 559 |
|
|
write_adr2 : out bus5;
|
| 560 |
|
|
write_GPR2 : out bus1;
|
| 561 |
|
|
--write_SCP2 : out bus1;
|
| 562 |
|
|
|
| 563 |
|
|
read_adr3 : out bus5;
|
| 564 |
|
|
read_adr4 : out bus5;
|
| 565 |
|
|
read_data3_GPR : in bus32;
|
| 566 |
|
|
read_data3_SCP : in bus32;
|
| 567 |
|
|
read_data4_GPR : in bus32;
|
| 568 |
|
|
read_data4_SCP : in bus32
|
| 569 |
|
|
);
|
| 570 |
|
|
end component;
|
| 571 |
|
|
|
| 572 |
|
|
|
| 573 |
|
|
component banc
|
| 574 |
|
|
port (
|
| 575 |
|
|
clock : in bus1;
|
| 576 |
|
|
clock2 : in bus1;
|
| 577 |
|
|
reset : bus1;
|
| 578 |
|
|
|
| 579 |
|
|
reg_src1 : in bus5;
|
| 580 |
|
|
reg_src2 : in bus5;
|
| 581 |
|
|
|
| 582 |
|
|
reg_dest : in bus5;
|
| 583 |
|
|
donnee : in bus32;
|
| 584 |
|
|
|
| 585 |
|
|
cmd_ecr : in bus1;
|
| 586 |
|
|
|
| 587 |
|
|
data_src1 : out bus32;
|
| 588 |
|
|
data_src2 : out bus32;
|
| 589 |
|
|
|
| 590 |
|
|
reg_src3 : in bus5;
|
| 591 |
|
|
reg_src4 : in bus5;
|
| 592 |
|
|
|
| 593 |
|
|
reg_dest2 : in bus5;
|
| 594 |
|
|
donnee2 : in bus32;
|
| 595 |
|
|
|
| 596 |
|
|
cmd_ecr2 : in bus1;
|
| 597 |
|
|
|
| 598 |
|
|
data_src3 : out bus32;
|
| 599 |
|
|
data_src4 : out bus32
|
| 600 |
|
|
);
|
| 601 |
|
|
end component;
|
| 602 |
|
|
|
| 603 |
|
|
|
| 604 |
|
|
component bus_ctrl01
|
| 605 |
|
|
port
|
| 606 |
|
|
(
|
| 607 |
|
|
clock : bus1;
|
| 608 |
|
|
reset : bus1;
|
| 609 |
|
|
|
| 610 |
|
|
interrupt : in std_logic;
|
| 611 |
|
|
|
| 612 |
|
|
adr_from_ei : in bus32;
|
| 613 |
|
|
instr_to_ei : out bus32;
|
| 614 |
|
|
req_from_mem : in bus1;
|
| 615 |
|
|
r_w_from_mem : in bus1;
|
| 616 |
|
|
adr_from_mem : in bus32;
|
| 617 |
|
|
data_from_mem : in bus32;
|
| 618 |
|
|
data_to_mem : out bus32;
|
| 619 |
|
|
|
| 620 |
|
|
req_to_ram : out std_logic;
|
| 621 |
|
|
adr_to_ram : out bus32;
|
| 622 |
|
|
r_w_to_ram : out bus1;
|
| 623 |
|
|
ack_from_ram : in bus1;
|
| 624 |
|
|
data_inout_ram : inout bus32;
|
| 625 |
|
|
|
| 626 |
|
|
stop_all : out bus1
|
| 627 |
|
|
);
|
| 628 |
|
|
end component;
|
| 629 |
|
|
|
| 630 |
|
|
component bus_ctrl02
|
| 631 |
|
|
port
|
| 632 |
|
|
(
|
| 633 |
|
|
clock : bus1;
|
| 634 |
|
|
reset : bus1;
|
| 635 |
|
|
|
| 636 |
|
|
interrupt : in std_logic;
|
| 637 |
|
|
|
| 638 |
|
|
adr_from_ei : in bus32;
|
| 639 |
|
|
instr_to_ei : out bus32;
|
| 640 |
|
|
req_from_mem : in bus1;
|
| 641 |
|
|
r_w_from_mem : in bus1;
|
| 642 |
|
|
adr_from_mem : in bus32;
|
| 643 |
|
|
data_from_mem : in bus32;
|
| 644 |
|
|
data_to_mem : out bus32;
|
| 645 |
|
|
|
| 646 |
|
|
req_to_ram : out std_logic;
|
| 647 |
|
|
adr_to_ram : out bus32;
|
| 648 |
|
|
r_w_to_ram : out bus1;
|
| 649 |
|
|
ack_from_ram : in bus1;
|
| 650 |
|
|
data_inout_ram : inout bus32;
|
| 651 |
|
|
|
| 652 |
|
|
stop_all : out bus1
|
| 653 |
|
|
);
|
| 654 |
|
|
end component;
|
| 655 |
|
|
|
| 656 |
|
|
component syscop
|
| 657 |
|
|
port
|
| 658 |
|
|
(
|
| 659 |
|
|
clock : in bus1;
|
| 660 |
|
|
reset : in bus1;
|
| 661 |
|
|
|
| 662 |
|
|
MEM_adr : in bus32;
|
| 663 |
|
|
MEM_exc_cause : in bus32;
|
| 664 |
|
|
MEM_it_ok : in bus1;
|
| 665 |
|
|
|
| 666 |
|
|
it_mat : in bus1;
|
| 667 |
|
|
|
| 668 |
|
|
interrupt : out bus1;
|
| 669 |
|
|
vecteur_it : out bus32;
|
| 670 |
|
|
|
| 671 |
|
|
write_data : in bus32;
|
| 672 |
|
|
write_adr : in bus5;
|
| 673 |
|
|
write_SCP : in bus1;
|
| 674 |
|
|
|
| 675 |
|
|
read_adr1 : in bus5;
|
| 676 |
|
|
read_adr2 : in bus5;
|
| 677 |
|
|
read_data1 : out bus32;
|
| 678 |
|
|
read_data2 : out bus32;
|
| 679 |
|
|
--mod
|
| 680 |
|
|
MEM_adr2 : in bus32;
|
| 681 |
|
|
MEM_exc_cause2 : in bus32;
|
| 682 |
|
|
MEM_it_ok2 : in bus1;
|
| 683 |
|
|
|
| 684 |
|
|
write_data2 : in bus32;
|
| 685 |
|
|
write_adr2 : in bus5;
|
| 686 |
|
|
write_SCP2 : in bus1;
|
| 687 |
|
|
|
| 688 |
|
|
read_adr3 : in bus5;
|
| 689 |
|
|
read_adr4 : in bus5;
|
| 690 |
|
|
read_data3 : out bus32;
|
| 691 |
|
|
read_data4 : out bus32
|
| 692 |
|
|
);
|
| 693 |
|
|
end component;
|
| 694 |
|
|
|
| 695 |
|
|
|
| 696 |
|
|
component minimips
|
| 697 |
|
|
port (
|
| 698 |
|
|
clock : in bus1;
|
| 699 |
|
|
clock2 : in bus1;
|
| 700 |
|
|
reset : in bus1;
|
| 701 |
|
|
|
| 702 |
|
|
ram_req : out bus1;
|
| 703 |
|
|
ram_adr : out bus32;
|
| 704 |
|
|
ram_r_w : out bus1;
|
| 705 |
|
|
ram_data : inout bus32;
|
| 706 |
|
|
ram_ack : in bus1;
|
| 707 |
|
|
|
| 708 |
|
|
ram_req2 : out bus1;
|
| 709 |
|
|
ram_adr2 : out bus32;
|
| 710 |
|
|
ram_r_w2 : out bus1;
|
| 711 |
|
|
ram_data2 : inout bus32;
|
| 712 |
|
|
ram_ack2 : in bus1;
|
| 713 |
|
|
|
| 714 |
|
|
it_mat : in bus1
|
| 715 |
|
|
);
|
| 716 |
|
|
end component;
|
| 717 |
|
|
|
| 718 |
|
|
end pack_mips;
|
