Subversion Repositories minimips_superscalar

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--                                                                      --

--                                                                      --

-- miniMIPS Superscalar Processor : Instruction extraction stage 2      --

-- based on miniMIPS Processor                                          --

--                                                                      --

--                                                                      --

-- Author : Miguel Cafruni                                              --

-- miguel_cafruni@hotmail.com                                           --

--                                                      December 2018   --

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library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.pack_mips.all;

entity pps_ei_2 is

port (

  clock : in std_logic;

  reset : in std_logic;

  clear : in std_logic;    -- Clear the pipeline stage

  stop_all2 : in std_logic; -- Evolution locking signal

  -- Asynchronous inputs

  stop_ei : in std_logic;  -- Lock the EI_adr and Ei_instr registers

  genop : in std_logic;    -- Send nops

  -- Bus controler interface

  CTE_instr : in bus32;    -- Instruction from the memory

  ETC_adr : out bus32;     -- Address to read in memory

  -- Synchronous inputs from PF stage

  PF_pc : in bus32;        -- Current value of the pc (desnecessario no EI2)

  -- Synchronous outputs to DI stage

  EI_instr : out bus32;    -- Read interface

  EI_adr : out bus32;      -- Address from the read instruction

  EI_it_ok : out std_logic -- Allow hardware interruptions

);

end pps_ei_2;

architecture rtl of pps_ei_2 is

begin

  ETC_adr <= PF_pc; -- Connexion of the PC to the memory address bus

  -- Set the results

  process (clock)

  begin

    if falling_edge(clock) then

      if reset='1' then

        EI_instr <= INS_NOP;

        EI_adr <= (others => '0');

        EI_it_ok <= '0';

      elsif stop_all2='0' then

        if clear='1' then

          -- Clear the stage

          EI_instr <= INS_NOP;

          EI_it_ok <= '0';

        elsif genop='1' and stop_ei='0' then

          -- Send a nop

          EI_instr <= INS_NOP;

          EI_it_ok <= '1';

        elsif stop_ei='0' then

          -- Normal evolution

          EI_adr <= PF_pc;

          EI_instr <= CTE_instr;

          EI_it_ok <= '1';

        end if;

      end if;

    end if;

  end process;

end rtl;