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[/] [minirisc/] [trunk/] [sim/] [run] - Blame information for rev 7

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#!/bin/csh
 
ncverilog                                                       \
                +define+TEST_BENCH                              \
                                                                \
                ../verilog/core/alu.v                           \
                ../verilog/core/presclr_wdt.v                   \
                ../verilog/core/risc_core.v                     \
                ../verilog/core/primitives.v                    \
                ../verilog/core/register_file.v                 \
                ../verilog/core/risc_core_top.v                 \
                ../verilog/testbench/prog_mem.v                 \
                ../verilog/testbench/test.v                     \
                                                                        \
                ../../generic_memories/rtl/verilog/generic_spram.v      \
                ../../generic_memories/rtl/verilog/generic_dpram.v

Line No.	Rev	Author	Line
1	5	rudi	`#!/bin/csh`
2
3			`ncverilog \`
4			`+define+TEST_BENCH \`
5			`\`
6			`../verilog/core/alu.v \`
7			`../verilog/core/presclr_wdt.v \`
8			`../verilog/core/risc_core.v \`
9			`../verilog/core/primitives.v \`
10			`../verilog/core/register_file.v \`
11			`../verilog/core/risc_core_top.v \`
12			`../verilog/testbench/prog_mem.v \`
13			`../verilog/testbench/test.v \`
14			`\`
15			`../../generic_memories/rtl/verilog/generic_spram.v \`
16			`../../generic_memories/rtl/verilog/generic_dpram.v`

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Subversion Repositories minirisc

[/] [minirisc/] [trunk/] [sim/] [run] - Blame information for rev 7