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<p><b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name: Mini-Risc core</font></b> </p>
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<p>(See change Log at bottom of page for changes/updates)</p>
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<P> </P>
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<p><font size="+1"><u>Description: </u></font></p>
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<p>This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57
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from Microchip. Additional information about the instruction set and capabilities
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can be found at: www.microchip.com</p>
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<p>
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</p>
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<p><u><font size="+1">Legal Notice</font></u></p>
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<p><font color="#FF0000">PIC, Microchip, etc. are Trademarks of Microchip Technology
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Inc. I have no idea if implementing this core will or will not violate patents,
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copyrights or cause any other type of lawsuits. I provide this core AS IS, without
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any warranties. If you decide to build this core, you are responsible for any
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legal resolutions, such as patents and copyrights, and perhaps others ....</font>
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<font color="#FF0000">This source files may be used and distributed without</font>
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<font color="#FF0000">restriction provided that all copyright statement are
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not</font> <font color="#FF0000">removed from the files and that any derivative
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work contains</font> <font color="#FF0000">the original copyright notices and
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the associated disclaimer.</font></p>
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<blockquote>
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<blockquote>
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<p><font face="Times"> <b><font color="#FF0000">THIS SOURCE FILES ARE PROVIDED
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"AS IS" AND WITHOUT ANY</font></b></font><br>
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<font color="#FF0000"><b><font face="Times">EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, WITHOUT<br>
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND</font></b></font><br>
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<font color="#FF0000"><b><font face="Times">FITNESS FOR A PARTICULAR PURPOSE.</font></b></font></p>
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</blockquote>
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</blockquote>
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<p> </p>
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<p><font size="+1"><u>Motivation</u><u></u></font></p>
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<ul>
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<li>A PIC compatible Microcontroller that runs a lot faster</li>
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<li>Synthesisable and technology independent design</li>
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<li>Separate (External to the core) Program Memory</li>
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<li>Options to extend the core<font face="Georgia, Times New Roman, Times, serif" size="+1">
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</font></li>
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</ul>
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<p><font size="+2"><u><font size="+1">Compatibility</font></u></font></p>
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<p>This design should be fully software compatible to the Microchip Implementation
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of the PIC 16C57, except for the following extensions:</p>
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<ul>
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<li>Port A is full 8 bits wide</li>
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<li>Hardware stack is 4 level deep [original 2 levels] (can be easily expanded)</li>
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<li>Executions of instructions that modify the PC has became a lot more expensive
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due to the pipeline and execution of instructions on every cycle. Any instruction
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that writes to the PC (PC as destination (f), call, goto, retlw) now takes
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4 cycles to execute (instead of 2 in the original implementation).<br>
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The 4 'skip' instructions, remain as in the original implementation: 1 cycle
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if not skipped, 2 cycles if skipped.</li>
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<li>Sampling of IO ports might be off</li>
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<li>Timer and watchdog might be off a few cycles<font size="+1"> </font></li>
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</ul>
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<p><font size="+2"><u><font size="+1">Performance</font></u></font><u></u></p>
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<ul>
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<li>Single cycle instruction execution, except as noted above for PC modifications.</li>
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<li>I estimate about 22K gates with the xilinx primitives, (excluding Register
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File and Program Memory). A Xilinx Vertex XCV100 can hold 4 of this cores
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and program memory, and still have some room left.</li>
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</ul>
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<p><font size="+2"><u><font size="+1">Implementing the Core</font></u></font></p>
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<p>The only file you should edit if you really want to implement this core, is
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the 'primitives.v' file. It contains all parts that can be optimized, depending
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on the technology used. It includes memories, and arithmetic modules. I added
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a primitives_xilinx,v file and xilinx_primitives.zip which contain primitives
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for xilinx.</p>
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<p></p>
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<p><font size="+1"><u>Status</u></font></p>
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<p>First version of the core is released. Included with the release is also a
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small test bench and several test programs written in assembly. MPLAB from Microchip,
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can be used to compile and develop additional code.</p>
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<p>The core can be downloaded from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a>
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or via <a href="/cvsmodule.shtml">cvsget</a> (use minirisc for module name)<font size="+1">
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</font></p>
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<p><font size="+1"><u>Development Tools</u></font></p>
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<p>A very nice(and free) development environment with a software simulator is
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provided by Microchip on their web site. This environment works only on PCs.
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Various free and chimerical tools are available from third party, just Search
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the web !</p>
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<p><a href="http://www.microchip.com/10/Tools/PICmicro/DevEnv/">Here is a link
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to the Microchip Development environment</a> (http://www.microchip.com/10/Tools/PICmicro/DevEnv/)</p>
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<p><font size="+1"><u>To-Do</u></font></p>
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<p>Things that need to be done</p>
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<ol>
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<li>Write more test/compliance test vectors
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<ul>
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<li> Verify that all instructions after a goto/call/retlw/write to PCL are
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not executed</li>
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<li> Verify ALU</li>
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<li> Timer and Watchdog tests</li>
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</ul>
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</li>
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<ul>
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<li> Perhaps some other areas ?</li>
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</ul>
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<li>Extensions ?
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<ul>
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<li> guess this is on a "as needed" basis</li>
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<li>Would be nice to extend the register file and have a few registers that
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are shared between two or more of this cores in a MP implementation !</li>
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</ul>
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</li>
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</ol>
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<p><font size="+2"><u><font size="+1">Author / Maintainer</font></u></font></p>
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<p>I have been doing ASIC design, verification and synthesis for over 15 years.
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This core is only a "midnight hack", and should be used with caution. I'd also
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like to know if anyone will actually use this core. Please send me a note if
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you will !</p>
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<p>Rudolf Usselmann <a href="mailto:rudi@asics.ws_NOSPAM">rudi@asics.ws_NOSPAM</a></p>
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<p>Feel free to send me comments, suggestions and bug reports.</p>
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<P><FONT FACE="Times"></FONT><font size="+2"><u><font size="+1">Change Log</font></u></font></P>
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<p>6/18/200 RU<br>
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- Added this Change Log<br>
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- Added "Development Tools" Section|<br>
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- Removed speed claims from the "Performance" Section: Need to re-synthsise
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the core and resolve synthesis tool/backend tool issues.<br>
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- added "risc_core_top.v", a top level with tri-state buffers and
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program memory, to make it look like a real PIC !<br>
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- Updated the primitives_xilinx.v so it will work correctly with Synplify and
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Synopsys FPGA compiler</p>
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