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philippe |
-------------------------------------------------------------------------------
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-- Title : UART
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-- Project : UART
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-------------------------------------------------------------------------------
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-- File : Uart.vhd
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-- Author : Philippe CARTON
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-- (pc@microsystemes.com / philippe.carton2@libertysurf.fr)
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-- Organization: Microsystemes
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-- Created : 15/12/2001
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-- Last update : 28/12/2001
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-- Platform : Foundation 3.1i
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-- Simulators : Foundation logic simulator
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-- Synthesizers: Foundation Synopsys
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-- Targets : Xilinx Spartan
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-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
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-------------------------------------------------------------------------------
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-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
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-- Wishbone compatable.
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-------------------------------------------------------------------------------
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-- Copyright (c) notice
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-- This core adheres to the GNU public license
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--
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number :
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-- Version :
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-- Date :
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-- Modifier : name <email>
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-- Description :
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity UART is
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generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor
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port (
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-- Wishbone signals
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WB_CLK_I : in Std_Logic; -- clock
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WB_RST_I : in Std_Logic; -- Reset input
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WB_ADR_I : in Std_Logic_Vector(1 downto 0); -- Adress bus
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WB_DAT_I : in Std_Logic_Vector(7 downto 0); -- DataIn Bus
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WB_DAT_O : out Std_Logic_Vector(7 downto 0); -- DataOut Bus
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WB_WE_I : in Std_Logic; -- Write Enable
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WB_STB_I : in Std_Logic; -- Strobe
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WB_ACK_O : out Std_Logic; -- Acknowledge
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-- process signals
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IntTx_O : out Std_Logic; -- Transmit interrupt: indicate waiting for Byte
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IntRx_O : out Std_Logic; -- Receive interrupt: indicate Byte received
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BR_Clk_I : in Std_Logic; -- Clock used for Transmit/Receive
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TxD_PAD_O: out Std_Logic; -- Tx RS232 Line
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RxD_PAD_I: in Std_Logic); -- Rx RS232 Line
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end entity;
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-- Architecture for UART for synthesis
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architecture Behaviour of UART is
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component Counter is
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generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
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port (
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Clk : in Std_Logic; -- Clock
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Reset : in Std_Logic; -- Reset input
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CE : in Std_Logic; -- Chip Enable
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O : out Std_Logic); -- Output
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end component;
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component RxUnit is
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port (
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Clk : in Std_Logic; -- system clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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ReadA : in Std_logic; -- Async Read Received Byte
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RxD : in Std_Logic; -- RS-232 data input
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RxAv : out Std_Logic; -- Byte available
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DataO : out Std_Logic_Vector(7 downto 0)); -- Byte received
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end component;
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component TxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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LoadA : in Std_Logic; -- Asynchronous Load
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TxD : out Std_Logic; -- RS-232 data output
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Busy : out Std_Logic; -- Tx Busy
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DataI : in Std_Logic_Vector(7 downto 0)); -- Byte to transmit
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end component;
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signal RxData : Std_Logic_Vector(7 downto 0); -- Last Byte received
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signal TxData : Std_Logic_Vector(7 downto 0); -- Last bytes transmitted
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signal SReg : Std_Logic_Vector(7 downto 0); -- Status register
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signal EnabRx : Std_Logic; -- Enable RX unit
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signal EnabTx : Std_Logic; -- Enable TX unit
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signal RxAv : Std_Logic; -- Data Received
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signal TxBusy : Std_Logic; -- Transmiter Busy
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signal ReadA : Std_Logic; -- Async Read receive buffer
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signal LoadA : Std_Logic; -- Async Load transmit buffer
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signal Sig0 : Std_Logic; -- gnd signal
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signal Sig1 : Std_Logic; -- vcc signal
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begin
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sig0 <= '0';
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sig1 <= '1';
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Uart_Rxrate : Counter -- Baud Rate adjust
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generic map (COUNT => BRDIVISOR)
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port map (BR_CLK_I, sig0, sig1, EnabRx);
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Uart_Txrate : Counter -- 4 Divider for Tx
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generic map (COUNT => 4)
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port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
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Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
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Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
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IntTx_O <= not TxBusy;
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IntRx_O <= RxAv;
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SReg(0) <= not TxBusy;
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SReg(1) <= RxAv;
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-- Implements WishBone data exchange.
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-- Clocked on rising edge. Synchronous Reset RST_I
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WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
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variable StatM : Std_Logic_Vector(4 downto 0);
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begin
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if Rising_Edge(WB_CLK_I) then
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if (WB_RST_I = '1') then
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ReadA <= '0';
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LoadA <= '0';
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else
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if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
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TxData <= WB_DAT_I;
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LoadA <= '1'; -- Load signal
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else LoadA <= '0';
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end if;
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if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
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ReadA <= '1'; -- Read signal
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else ReadA <= '0';
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end if;
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end if;
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end if;
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end process;
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WB_ACK_O <= WB_STB_I;
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WB_DAT_O <=
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RxData when WB_ADR_I = "00" else -- Read Byte from Rx
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SReg when WB_ADR_I = "01" else -- Read Status Reg
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X"00";
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end Behaviour;
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