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Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [impl/] [Xilinx/] [log/] [map.rtf] - Blame information for rev 26

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1 14 philippe 
{\rtf1\ansi\ansicpg1252\deff0\deflang1036{\fonttbl {\f0\fnil\fcharset0 Courier New;}}
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{\colortbl ;\red255\green0\blue0;}
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\uc1\pard\ulnone\f0\fs20 Release 3.1i - Par D.19\par
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\par
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Sat May 04 18:33:07 2002\par
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\par
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par -w -ol 2 -d 0 map.ncd uartimpl.ncd uartimpl.pcf\par
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\par
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\par
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Constraints file: uartimpl.pcf\par
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\par
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Loading device database for application par from file "map.ncd".\par
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   "uartimpl" is an NCD, version 2.32, device xcs10, package tq144, speed -3\par
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Loading device for application par from file '4005e.nph' in environment\par
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C:/Fndtn.\par
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Device speed data version:  x1_0.14.2.2 1.7 PRELIMINARY.\par
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\par
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\par
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\cf1 Device utilization summary:\par
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\par
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   Number of External IOBs            28 out of 112    25%\par
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      Flops:                           0\par
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      Latches:                         0\par
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   Number of IOBs driving Global Buffers    2 out of 8      25%\par
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\par
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   Number of CLBs                     44 out of 196    22%\par
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      Total CLB Flops:                63 out of 392    16%\par
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      4 input LUTs:                   63 out of 392    16%\par
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      3 input LUTs:                   20 out of 196    10%\par
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\par
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   Number of PRI-CLKs                  2 out of 4      50%\cf0\par
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\par
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\par
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\par
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Overall effort level (-ol):   2 (set by user)\par
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Placer effort level (-pl):    2 (set by user)\par
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Placer cost table entry (-t): 1\par
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Router effort level (-rl):    2 (set by user)\par
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\par
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Starting initial Placement phase.  REAL time: 0 secs \par
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Finished initial Placement phase.  REAL time: 0 secs \par
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\par
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Starting Constructive Placer.  REAL time: 0 secs \par
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Placer score = 68880\par
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Placer score = 44100\par
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Placer score = 35940\par
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Placer score = 32580\par
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Placer score = 28320\par
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Placer score = 27540\par
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Placer score = 26760\par
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Placer score = 25740\par
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Placer score = 25080\par
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Placer score = 25020\par
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Placer score = 24840\par
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Placer score = 24600\par
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Placer score = 24180\par
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Placer score = 24060\par
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Finished Constructive Placer.  REAL time: 2 secs \par
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\par
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Writing design to file "uartimpl.ncd".\par
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\par
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Starting Optimizing Placer.  REAL time: 2 secs \par
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Optimizing  \par
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Swapped 26 comps.\par
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Xilinx Placer [1]   22320   REAL time: 2 secs \par
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\par
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Finished Optimizing Placer.  REAL time: 2 secs \par
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\par
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Writing design to file "uartimpl.ncd".\par
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\par
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Total REAL time to Placer completion: 2 secs \par
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Total CPU time to Placer completion: 2 secs \par
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\par
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Starting router resource preassignment\par
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Completed router resource preassignment. REAL time: 2 secs \par
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Starting iterative routing. \par
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Routing active signals.\par
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End of iteration 1 \par
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315 successful; 0 unrouted active,\par
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   3 unrouted PWR/GND; (0) REAL time: 3 secs \par
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End of iteration 2 \par
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315 successful; 0 unrouted active,\par
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   3 unrouted PWR/GND; (0) REAL time: 3 secs \par
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Constraints are met. \par
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Routing PWR/GND nets.\par
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Power and ground nets completely routed. \par
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Writing design to file "uartimpl.ncd".\par
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Starting cleanup \par
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Improving routing.\par
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End of cleanup iteration 1 \par
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318 successful; 0 unrouted; (0) REAL time: 4 secs \par
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Writing design to file "uartimpl.ncd".\par
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Total REAL time: 4 secs \par
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Total CPU  time: 4 secs \par
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End of route.  318 routed (100.00%); 0 unrouted.\par
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No errors found. \par
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Completely routed. \par
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\par
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This design was run without timing constraints.  It is likely that much better\par
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circuit performance can be obtained by trying either or both of the following:\par
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\par
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  - Enabling the Delay Based Cleanup router pass, if not already enabled\par
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  - Supplying timing constraints in the input design\par
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\par
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\par
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Total REAL time to Router completion: 4 secs \par
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Total CPU time to Router completion: 4 secs \par
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\par
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Generating PAR statistics.\par
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\par
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   The Delay Summary Report\par
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\par
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   The Score for this design is: 306\par
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\par
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\par
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The Number of signals not completely routed for this design is: 0\par
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\par
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   The Average Connection Delay for this design is:        2.041 ns\par
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   The Maximum Pin Delay is:                               9.391 ns\par
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   The Average Connection Delay on the 10 Worst Nets is:   5.097 ns\par
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\par
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   Listing Pin Delays by value: (ns)\par
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\par
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    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 10.00  d >= 10.00\par
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   ---------   ---------   ---------   ---------   ---------   ---------\par
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         202          89          25           0           2           0\par
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\par
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Writing design to file "uartimpl.ncd".\par
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\par
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\par
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All signals are completely routed.\par
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\par
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Total REAL time to PAR completion: 4 secs \par
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Total CPU time to PAR completion: 5 secs \par
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\par
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Placement: Completed - No errors found.\par
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Routing: Completed - No errors found.\par
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\par
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PAR done.\par
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\par
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}
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