URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

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[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [__projnav.log] - Blame information for rev 26

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ISE Auto-Make Log File
-----------------------
 
Updating: Analyze Post-Place & Route Static Timing (Timing Analyzer)
 
Starting: 'exewrap -tapkeep -mode pipe -tcl -command e:/ise/data/projnav/_filesAllClean.tcl _XSTClean.rsp 0'
 
 
Creating TCL Process
Cleaning Up Project
Finished cleaning up project
Done: completed successfully.
 
Starting: 'exewrap -mode pipe -tapkeep -command e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr'
 
 
Starting: 'e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr '
 
 
Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VHDL
Input File Name                    : uart.prj
 
---- Target Parameters
Target Device                      : xc2s15-cs144-6
Output File Name                   : uart
Output Format                      : NGC
Target Technology                  : spartan2
 
---- Source Options
Entity Name                        : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6
 
---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
 
=========================================================================
 
Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work.
Entity  (Architecture ) compiled.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work.
Entity  (Architecture ) compiled.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing generic Entity  (Architecture ).
        count = 130
Entity  analyzed. Unit  generated.
 
Analyzing generic Entity  (Architecture ).
        count = 4
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred   3 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd.
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 2-bit adder for signal <$n0002> created at line 91.
    Found 4-bit adder for signal <$n0018> created at line 85.
    Found 4-bit comparator greatequal for signal <$n0038> created at line 81.
    Found 4-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 2-bit register for signal .
    Summary:
        inferred  24 D-type flip-flop(s).
        inferred   2 Adder/Subtracter(s).
        inferred   1 Comparator(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/Txunit.vhd.
    Found 1-bit register for signal .
    Found 4-bit adder for signal <$n0012> created at line 92.
    Found 4-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtracter(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 2-bit down counter for signal .
WARNING:Xst:647 - Input  is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 8-bit down counter for signal .
WARNING:Xst:647 - Input  is never used.
WARNING:Xst:647 - Input  is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/miniuart.vhd.
WARNING:Xst:646 - Signal  is assigned but never used.
WARNING:Xst:646 - Signal  is assigned but never used.
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Summary:
        inferred  10 D-type flip-flop(s).
Unit  synthesized.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Registers                        : 26
  4-bit register                   : 2
  2-bit register                   : 1
  8-bit register                   : 4
  1-bit register                   : 19
# Counters                         : 2
  2-bit down counter               : 1
  8-bit down counter               : 1
# Adders/Subtractors               : 3
  2-bit adder                      : 1
  4-bit adder                      : 2
# Comparators                      : 1
  4-bit comparator greatequal      : 1
 
=========================================================================
 
 
Starting low level synthesis...
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Building and optimizing final netlist ...
 
FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute.
=========================================================================
Final Results
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+
 
Macro Statistics
# Registers                        : 35
  4-bit register                   : 2
  8-bit register                   : 4
  2-bit register                   : 2
  1-bit register                   : 27
# Adders/Subtractors               : 3
  4-bit adder                      : 2
  8-bit subtractor                 : 1
 
Design Statistics
# IOs                              : 28
 
Cell Usage :
# BELS                             : 153
#      GND                         : 1
#      LUT1                        : 13
#      LUT1_D                      : 2
#      LUT1_L                      : 3
#      LUT2                        : 21
#      LUT3                        : 24
#      LUT3_L                      : 2
#      LUT4                        : 51
#      LUT4_D                      : 2
#      LUT4_L                      : 2
#      MUXCY                       : 13
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 14
# FlipFlops/Latches                : 72
#      FDC                         : 4
#      FDCE                        : 10
#      FDE                         : 40
#      FDPE                        : 1
#      FDR                         : 11
#      FDRE                        : 2
#      FDS                         : 2
#      FDSE                        : 2
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 26
#      IBUF                        : 14
#      OBUF                        : 12
=========================================================================
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
uart_rxunit_rregl:Q                | NONE                   | 3     |
br_clk_i                           | BUFGP                  | 59    |
loada:Q                            | NONE                   | 1     |
wb_clk_i                           | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -6
 
   Minimum period: 9.318ns (Maximum Frequency: 107.319MHz)
   Minimum input arrival time before clock: 8.430ns
   Maximum output required time after clock: 10.658ns
   Maximum combinational path delay: 9.098ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'br_clk_i'
Delay:               9.318ns (Levels of Logic = 6)
  Source:            uart_rxunit_bitpos_0
  Destination:       uart_rxunit_bitpos_2
  Source Clock:      br_clk_i rising
  Destination Clock: br_clk_i rising
 
  Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q             22   1.085   2.970  uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0)
    LUT1_D:I0->LO          1   0.549   0.000  uart_rxunit_Madd__n0018_inst_lut2_0 (N3009)
    MUXCY:S->O             1   0.659   0.000  uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0)
    MUXCY:CI->O            1   0.042   0.000  uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1)
    XORCY:CI->O            1   0.420   1.035  uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181)
    LUT4:I3->O             1   0.549   1.035  uart_rxunit_I_10_LUT_53 (uart_rxunit_N183)
    LUT4_L:I0->LO          1   0.549   0.000  uart_rxunit_I__n0005_2 (uart_rxunit_N201)
    FDCE:D                     0.425          uart_rxunit_bitpos_2
    ----------------------------------------
    Total                      9.318ns (4.278ns logic, 5.040ns route)
                                       (45.9% logic, 54.1% route)
 
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i'
Offset:              8.430ns (Levels of Logic = 3)
  Source:            wb_rst_i
  Destination:       uart_txunit_treg_5
  Destination Clock: br_clk_i rising
 
  Data Path: wb_rst_i to uart_txunit_treg_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             19   0.776   2.790  wb_rst_i_IBUF (wb_rst_i_IBUF)
    LUT4:I3->O             1   0.549   1.035  uart_txunit_I_1_LUT_11 (N2973)
    LUT4:I3->O             8   0.549   1.845  uart_txunit_I__n0009 (uart_txunit_N83)
    FDE:CE                     0.886          uart_txunit_treg_5
    ----------------------------------------
    Total                      8.430ns (2.760ns logic, 5.670ns route)
                                       (32.7% logic, 67.3% route)
 
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i'
Offset:              10.658ns (Levels of Logic = 3)
  Source:            uart_txunit_tbufl
  Destination:       wb_dat_o_0
  Source Clock:      br_clk_i rising
 
  Data Path: uart_txunit_tbufl to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q              5   1.085   1.566  uart_txunit_tbufl (uart_txunit_tbufl)
    LUT2:I1->O             2   0.549   1.206  uart_txunit_I_busy (N64)
    LUT4:I2->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                     10.658ns (6.851ns logic, 3.807ns route)
                                       (64.3% logic, 35.7% route)
 
-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.098ns (Levels of Logic = 3)
  Source:            wb_adr_i_1
  Destination:       wb_dat_o_0
 
  Data Path: wb_adr_i_1 to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             11   0.776   2.070  wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)
    LUT4:I0->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                      9.098ns (5.993ns logic, 3.105ns route)
                                       (65.9% logic, 34.1% route)
 
=========================================================================
CPU : 9.22 / 9.67 s | Elapsed : 10.00 / 10.00 s
 
-->
EXEWRAP detected that program 'e:/ise/bin/nt/xst.exe' completed successfully.
 
Done: completed successfully.
 
Starting: 'exewrap @__ednTOngd_exewrap.rsp'
 
 
Starting: 'ngdbuild -f __ngdbuild.rsp '
 
 
Release 4.2i - ngdbuild E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
 
Command Line: ngdbuild -dd j:/impl/_ngo -nt timestamp -p xc2s15-cs144-6 uart.ngc
uart.ngd
 
Reading NGO file "J:/impl/uart.ngc" ...
Reading component libraries for design expansion...
 
Checking timing specifications ...
Checking expanded design ...
 
NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0
 
Writing NGD file "uart.ngd" ...
 
Writing NGDBUILD log file "uart.bld"...
 
NGDBUILD done.
EXEWRAP detected that program 'ngdbuild' completed successfully.
 
Done: completed successfully.
 
Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'
 
 
Creating TCL Process
Starting: 'map -f _map.rsp'
 
 
Release 4.2i - Map E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Using target part "2s15cs144-6".
Removing unused or disabled logic...
Running cover...
Writing file uart.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "uart.ncd"...
 
Design Summary:
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                 83 out of    192   43%
   Number of Slices containing
      unrelated logic:                0 out of     83    0%
   Number of Slice Flip Flops:       63 out of    384   16%
   Total Number 4 input LUTs:       115 out of    384   29%
      Number used as LUTs:                        110
      Number used as a route-thru:                  5
   Number of bonded IOBs:            26 out of     86   30%
      IOB Flip Flops:                               9
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
Total equivalent gate count for design:  1,329
Additional JTAG gate count for IOBs:  1,344
 
Mapping completed.
See MAP report file "uart.mrp" for details.
Tcl e:/ise/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.
 
Done: completed successfully.
 
Starting: 'exewrap @_nc1TOncd_exewrap.rsp'
 
 
Creating TCL Process
Found _prepar.rsp
Starting: 'par -f _par.rsp'
 
 
Release 4.2i - Par E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
 
 
WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".
 
 
Constraints file: uart.pcf
 
Loading design for application par from file par_temp.ncd.
   "uart" is an NCD, version 2.37, device xc2s15, package cs144, speed -6
Loading device for application par from file '2s15.nph' in environment e:/ise.
Device speed data version:  PRELIMINARY 1.23 2001-12-19.
 
 
Resolving physical constraints.
Finished resolving physical constraints.
 
Device utilization summary:
 
   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            26 out of 86     30%
      Number of LOCed External IOBs    0 out of 26      0%
 
   Number of SLICEs                   83 out of 192    43%
 
   Number of GCLKs                     2 out of 4      50%
 
 
 
Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)
 
Starting initial Placement phase. REAL time: 0 secs
Finished initial Placement phase. REAL time: 0 secs
Starting the placer. REAL time: 0 secs
Placement pass 1 ....
Placer score = 7875
Placement pass 2 ...............
Placer score = 7375
Optimizing ...
Placer score = 6385
Placer score = 5890
Placer completed in real time: 0 secs
 
Dumping design to file uart.ncd.
 
Total REAL time to Placer completion: 0 secs
Total CPU time to Placer completion: 1 secs
 
 
Starting router resource preassignment
Completed router resource preassignment. REAL time: 0 secs
Starting iterative routing.
Routing active signals.
.....
End of iteration 1
526 successful; 0 unrouted; (0) REAL time: 0 secs
Constraints are met.
Total REAL time: 2 secs
Total CPU  time: 1 secs
End of route.  526 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.
 
This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:
 
  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design
 
 
Total REAL time to Router completion: 2 secs
Total CPU time to Router completion: 1 secs
 
Generating PAR statistics.
Dumping design to file uart.ncd.
 
 
All signals are completely routed.
 
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 1 secs
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
 
PAR done.
Tcl e:/ise/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.
 
PAR completed successfully
Done: completed successfully.
 
Launching: 'exewrap -tcl -command __launchTA.tcl'
 
 
 
ISE Auto-Make Log File
-----------------------
 
Starting: 'jhdparse @Rxunit.jp'
 
 
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved.
 
Scanning    j:/rtl/vhdl/Rxunit.vhd
Scanning    j:/rtl/vhdl/Rxunit.vhd
Writing Rxunit.jhd.
 
JHDPARSE complete -    0 errors,    0 warnings.
 
Done: completed successfully.
 
Starting: 'jhdparse @Txunit.jp'
 
 
 
Starting: 'jhdparse @utils.jp'
 
 
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved.
 
Scanning    j:/rtl/vhdl/utils.vhd
Scanning    j:/rtl/vhdl/utils.vhd
j:/rtl/vhdl/utils.vhd(47) library IEEE,STD;
                                         ^
Warning 0008: Unable to open library std.
Writing utils.jhd.
 
JHDPARSE complete -    0 errors,    1 warning.
 
Done: completed successfully.
 
Starting: 'jhdparse @miniuart.jp'
 
 
 

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Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [__projnav.log] - Blame information for rev 26

Line No.	Rev	Author	Line
1	22	philippe	`ISE Auto-Make Log File`
2			`-----------------------`
3
4			`Updating: Analyze Post-Place & Route Static Timing (Timing Analyzer)`
5
6			`Starting: 'exewrap -tapkeep -mode pipe -tcl -command e:/ise/data/projnav/_filesAllClean.tcl _XSTClean.rsp 0'`
7
8
9			`Creating TCL Process`
10			`Cleaning Up Project`
11			`Finished cleaning up project`
12			`Done: completed successfully.`
13
14			`Starting: 'exewrap -mode pipe -tapkeep -command e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr'`
15
16
17			`Starting: 'e:/ise/bin/nt/xst.exe -ifn uart.xst -ofn uart.syr '`
18
19
20			`Release 4.2i - xst E.35`
21			`Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.`
22			`--> Parameter TMPDIR set to .`
23			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
24
25			`--> Parameter overwrite set to YES`
26			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
27
28			`--> Parameter xsthdpdir set to ./xst`
29			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
30
31			`--> =========================================================================`
32			`---- Source Parameters`
33			`Input Format : VHDL`
34			`Input File Name : uart.prj`
35
36			`---- Target Parameters`
37			`Target Device : xc2s15-cs144-6`
38			`Output File Name : uart`
39			`Output Format : NGC`
40			`Target Technology : spartan2`
41
42			`---- Source Options`
43			`Entity Name : uart`
44			`Automatic FSM Extraction : YES`
45			`FSM Encoding Algorithm : Auto`
46			`FSM Flip-Flop Type : D`
47			`Mux Extraction : YES`
48			`Resource Sharing : YES`
49			`Complex Clock Enable Extraction : YES`
50			`ROM Extraction : Yes`
51			`RAM Extraction : Yes`
52			`RAM Style : Auto`
53			`Mux Style : Auto`
54			`Decoder Extraction : YES`
55			`Priority Encoder Extraction : YES`
56			`Shift Register Extraction : YES`
57			`Logical Shifter Extraction : YES`
58			`XOR Collapsing : YES`
59			`Automatic Register Balancing : No`
60
61			`---- Target Options`
62			`Add IO Buffers : YES`
63			`Equivalent register Removal : YES`
64			`Add Generic Clock Buffer(BUFG) : 4`
65			`Global Maximum Fanout : 100`
66			`Register Duplication : YES`
67			`Move First FlipFlop Stage : YES`
68			`Move Last FlipFlop Stage : YES`
69			`Slice Packing : YES`
70			`Pack IO Registers into IOBs : auto`
71			`Speed Grade : 6`
72
73			`---- General Options`
74			`Optimization Criterion : Speed`
75			`Optimization Effort : 1`
76			`Check Attribute Syntax : YES`
77			`Keep Hierarchy : No`
78			`Global Optimization : AllClockNets`
79			`Write Timing Constraints : No`
80
81			`=========================================================================`
82
83			`Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work.`
84			`Entity (Architecture ) compiled.`
85			`Entity (Architecture ) compiled.`
86			`Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work.`
87			`Entity (Architecture ) compiled.`
88			`Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work.`
89			`Entity (Architecture ) compiled.`
90			`Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work.`
91			`Entity (Architecture ) compiled.`
92
93			`Analyzing Entity (Architecture ).`
94			`Entity analyzed. Unit generated.`
95
96			`Analyzing generic Entity (Architecture ).`
97			`count = 130`
98			`Entity analyzed. Unit generated.`
99
100			`Analyzing generic Entity (Architecture ).`
101			`count = 4`
102			`Entity analyzed. Unit generated.`
103
104			`Analyzing Entity (Architecture ).`
105			`Entity analyzed. Unit generated.`
106
107			`Analyzing Entity (Architecture ).`
108			`Entity analyzed. Unit generated.`
109
110			`Analyzing Entity (Architecture ).`
111			`Entity analyzed. Unit generated.`
112
113
114			`Synthesizing Unit .`
115			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
116			`Found 1-bit register for signal .`
117			`Found 1-bit register for signal .`
118			`Found 1-bit register for signal .`
119			`Summary:`
120			`inferred 3 D-type flip-flop(s).`
121			`Unit synthesized.`
122
123
124			`Synthesizing Unit .`
125			`Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd.`
126			`Found 1-bit register for signal .`
127			`Found 8-bit register for signal .`
128			`Found 2-bit adder for signal <$n0002> created at line 91.`
129			`Found 4-bit adder for signal <$n0018> created at line 85.`
130			`Found 4-bit comparator greatequal for signal <$n0038> created at line 81.`
131			`Found 4-bit register for signal .`
132			`Found 8-bit register for signal .`
133			`Found 1-bit register for signal .`
134			`Found 2-bit register for signal .`
135			`Summary:`
136			`inferred 24 D-type flip-flop(s).`
137			`inferred 2 Adder/Subtracter(s).`
138			`inferred 1 Comparator(s).`
139			`Unit synthesized.`
140
141
142			`Synthesizing Unit .`
143			`Related source file is J:/impl/../rtl/vhdl/Txunit.vhd.`
144			`Found 1-bit register for signal .`
145			`Found 4-bit adder for signal <$n0012> created at line 92.`
146			`Found 4-bit register for signal .`
147			`Found 8-bit register for signal .`
148			`Found 1-bit register for signal .`
149			`Found 8-bit register for signal .`
150			`Summary:`
151			`inferred 22 D-type flip-flop(s).`
152			`inferred 1 Adder/Subtracter(s).`
153			`Unit synthesized.`
154
155
156			`Synthesizing Unit .`
157			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
158			`Found 1-bit register for signal .`
159			`Found 2-bit down counter for signal .`
160			`WARNING:Xst:647 - Input is never used.`
161			`Summary:`
162			`inferred 1 Counter(s).`
163			`inferred 1 D-type flip-flop(s).`
164			`Unit synthesized.`
165
166
167			`Synthesizing Unit .`
168			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
169			`Found 1-bit register for signal .`
170			`Found 8-bit down counter for signal .`
171			`WARNING:Xst:647 - Input is never used.`
172			`WARNING:Xst:647 - Input is never used.`
173			`Summary:`
174			`inferred 1 Counter(s).`
175			`inferred 1 D-type flip-flop(s).`
176			`Unit synthesized.`
177
178
179			`Synthesizing Unit .`
180			`Related source file is J:/impl/../rtl/vhdl/miniuart.vhd.`
181			`WARNING:Xst:646 - Signal is assigned but never used.`
182			`WARNING:Xst:646 - Signal is assigned but never used.`
183			`Found 1-bit register for signal .`
184			`Found 1-bit register for signal .`
185			`Found 8-bit register for signal .`
186			`Summary:`
187			`inferred 10 D-type flip-flop(s).`
188			`Unit synthesized.`
189
190			`=========================================================================`
191			`HDL Synthesis Report`
192
193			`Macro Statistics`
194			`# Registers : 26`
195			`4-bit register : 2`
196			`2-bit register : 1`
197			`8-bit register : 4`
198			`1-bit register : 19`
199			`# Counters : 2`
200			`2-bit down counter : 1`
201			`8-bit down counter : 1`
202			`# Adders/Subtractors : 3`
203			`2-bit adder : 1`
204			`4-bit adder : 2`
205			`# Comparators : 1`
206			`4-bit comparator greatequal : 1`
207
208			`=========================================================================`
209
210
211			`Starting low level synthesis...`
212			`Optimizing unit ...`
213
214			`Optimizing unit ...`
215
216			`Optimizing unit ...`
217
218			`Optimizing unit ...`
219
220			`Building and optimizing final netlist ...`
221
222			`FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute.`
223			`=========================================================================`
224			`Final Results`
225			`Top Level Output File Name : uart`
226			`Output Format : NGC`
227			`Optimization Criterion : Speed`
228			`Target Technology : spartan2`
229			`Keep Hierarchy : No`
230			`Macro Generator : macro+`
231
232			`Macro Statistics`
233			`# Registers : 35`
234			`4-bit register : 2`
235			`8-bit register : 4`
236			`2-bit register : 2`
237			`1-bit register : 27`
238			`# Adders/Subtractors : 3`
239			`4-bit adder : 2`
240			`8-bit subtractor : 1`
241
242			`Design Statistics`
243			`# IOs : 28`
244
245			`Cell Usage :`
246			`# BELS : 153`
247			`# GND : 1`
248			`# LUT1 : 13`
249			`# LUT1_D : 2`
250			`# LUT1_L : 3`
251			`# LUT2 : 21`
252			`# LUT3 : 24`
253			`# LUT3_L : 2`
254			`# LUT4 : 51`
255			`# LUT4_D : 2`
256			`# LUT4_L : 2`
257			`# MUXCY : 13`
258			`# MUXF5 : 4`
259			`# VCC : 1`
260			`# XORCY : 14`
261			`# FlipFlops/Latches : 72`
262			`# FDC : 4`
263			`# FDCE : 10`
264			`# FDE : 40`
265			`# FDPE : 1`
266			`# FDR : 11`
267			`# FDRE : 2`
268			`# FDS : 2`
269			`# FDSE : 2`
270			`# Clock Buffers : 2`
271			`# BUFGP : 2`
272			`# IO Buffers : 26`
273			`# IBUF : 14`
274			`# OBUF : 12`
275			`=========================================================================`
276
277
278			`=========================================================================`
279			`TIMING REPORT`
280
281			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
282			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
283			`GENERATED AFTER PLACE-and-ROUTE.`
284
285			`Clock Information:`
286			`------------------`
287			`-----------------------------------+------------------------+-------+`
288			`Clock Signal \| Clock buffer(FF name) \| Load \|`
289			`-----------------------------------+------------------------+-------+`
290			`uart_rxunit_rregl:Q \| NONE \| 3 \|`
291			`br_clk_i \| BUFGP \| 59 \|`
292			`loada:Q \| NONE \| 1 \|`
293			`wb_clk_i \| BUFGP \| 10 \|`
294			`-----------------------------------+------------------------+-------+`
295
296			`Timing Summary:`
297			`---------------`
298			`Speed Grade: -6`
299
300			`Minimum period: 9.318ns (Maximum Frequency: 107.319MHz)`
301			`Minimum input arrival time before clock: 8.430ns`
302			`Maximum output required time after clock: 10.658ns`
303			`Maximum combinational path delay: 9.098ns`
304
305			`Timing Detail:`
306			`--------------`
307			`All values displayed in nanoseconds (ns)`
308
309			`-------------------------------------------------------------------------`
310			`Timing constraint: Default period analysis for Clock 'br_clk_i'`
311			`Delay: 9.318ns (Levels of Logic = 6)`
312			`Source: uart_rxunit_bitpos_0`
313			`Destination: uart_rxunit_bitpos_2`
314			`Source Clock: br_clk_i rising`
315			`Destination Clock: br_clk_i rising`
316
317			`Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2`
318			`Gate Net`
319			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
320			`---------------------------------------- ------------`
321			`FDCE:C->Q 22 1.085 2.970 uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0)`
322			`LUT1_D:I0->LO 1 0.549 0.000 uart_rxunit_Madd__n0018_inst_lut2_0 (N3009)`
323			`MUXCY:S->O 1 0.659 0.000 uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0)`
324			`MUXCY:CI->O 1 0.042 0.000 uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1)`
325			`XORCY:CI->O 1 0.420 1.035 uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181)`
326			`LUT4:I3->O 1 0.549 1.035 uart_rxunit_I_10_LUT_53 (uart_rxunit_N183)`
327			`LUT4_L:I0->LO 1 0.549 0.000 uart_rxunit_I__n0005_2 (uart_rxunit_N201)`
328			`FDCE:D 0.425 uart_rxunit_bitpos_2`
329			`----------------------------------------`
330			`Total 9.318ns (4.278ns logic, 5.040ns route)`
331			`(45.9% logic, 54.1% route)`
332
333			`-------------------------------------------------------------------------`
334			`Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i'`
335			`Offset: 8.430ns (Levels of Logic = 3)`
336			`Source: wb_rst_i`
337			`Destination: uart_txunit_treg_5`
338			`Destination Clock: br_clk_i rising`
339
340			`Data Path: wb_rst_i to uart_txunit_treg_5`
341			`Gate Net`
342			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
343			`---------------------------------------- ------------`
344			`IBUF:I->O 19 0.776 2.790 wb_rst_i_IBUF (wb_rst_i_IBUF)`
345			`LUT4:I3->O 1 0.549 1.035 uart_txunit_I_1_LUT_11 (N2973)`
346			`LUT4:I3->O 8 0.549 1.845 uart_txunit_I__n0009 (uart_txunit_N83)`
347			`FDE:CE 0.886 uart_txunit_treg_5`
348			`----------------------------------------`
349			`Total 8.430ns (2.760ns logic, 5.670ns route)`
350			`(32.7% logic, 67.3% route)`
351
352			`-------------------------------------------------------------------------`
353			`Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i'`
354			`Offset: 10.658ns (Levels of Logic = 3)`
355			`Source: uart_txunit_tbufl`
356			`Destination: wb_dat_o_0`
357			`Source Clock: br_clk_i rising`
358
359			`Data Path: uart_txunit_tbufl to wb_dat_o_0`
360			`Gate Net`
361			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
362			`---------------------------------------- ------------`
363			`FDCE:C->Q 5 1.085 1.566 uart_txunit_tbufl (uart_txunit_tbufl)`
364			`LUT2:I1->O 2 0.549 1.206 uart_txunit_I_busy (N64)`
365			`LUT4:I2->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF)`
366			`OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0)`
367			`----------------------------------------`
368			`Total 10.658ns (6.851ns logic, 3.807ns route)`
369			`(64.3% logic, 35.7% route)`
370
371			`-------------------------------------------------------------------------`
372			`Timing constraint: Default path analysis`
373			`Delay: 9.098ns (Levels of Logic = 3)`
374			`Source: wb_adr_i_1`
375			`Destination: wb_dat_o_0`
376
377			`Data Path: wb_adr_i_1 to wb_dat_o_0`
378			`Gate Net`
379			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
380			`---------------------------------------- ------------`
381			`IBUF:I->O 11 0.776 2.070 wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)`
382			`LUT4:I0->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF)`
383			`OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0)`
384			`----------------------------------------`
385			`Total 9.098ns (5.993ns logic, 3.105ns route)`
386			`(65.9% logic, 34.1% route)`
387
388			`=========================================================================`
389			`CPU : 9.22 / 9.67 s \| Elapsed : 10.00 / 10.00 s`
390
391			`-->`
392			`EXEWRAP detected that program 'e:/ise/bin/nt/xst.exe' completed successfully.`
393
394			`Done: completed successfully.`
395
396			`Starting: 'exewrap @__ednTOngd_exewrap.rsp'`
397
398
399			`Starting: 'ngdbuild -f __ngdbuild.rsp '`
400
401
402			`Release 4.2i - ngdbuild E.35`
403			`Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.`
404
405			`Command Line: ngdbuild -dd j:/impl/_ngo -nt timestamp -p xc2s15-cs144-6 uart.ngc`
406			`uart.ngd`
407
408			`Reading NGO file "J:/impl/uart.ngc" ...`
409			`Reading component libraries for design expansion...`
410
411			`Checking timing specifications ...`
412			`Checking expanded design ...`
413
414			`NGDBUILD Design Results Summary:`
415			`Number of errors: 0`
416			`Number of warnings: 0`
417
418			`Writing NGD file "uart.ngd" ...`
419
420			`Writing NGDBUILD log file "uart.bld"...`
421
422			`NGDBUILD done.`
423			`EXEWRAP detected that program 'ngdbuild' completed successfully.`
424
425			`Done: completed successfully.`
426
427			`Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'`
428
429
430			`Creating TCL Process`
431			`Starting: 'map -f _map.rsp'`
432
433
434			`Release 4.2i - Map E.35`
435			`Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.`
436			`Using target part "2s15cs144-6".`
437			`Removing unused or disabled logic...`
438			`Running cover...`
439			`Writing file uart.ngm...`
440			`Running directed packing...`
441			`Running delay-based packing...`
442			`Running related packing...`
443			`Writing design file "uart.ncd"...`
444
445			`Design Summary:`
446			`Number of errors: 0`
447			`Number of warnings: 0`
448			`Number of Slices: 83 out of 192 43%`
449			`Number of Slices containing`
450			`unrelated logic: 0 out of 83 0%`
451			`Number of Slice Flip Flops: 63 out of 384 16%`
452			`Total Number 4 input LUTs: 115 out of 384 29%`
453			`Number used as LUTs: 110`
454			`Number used as a route-thru: 5`
455			`Number of bonded IOBs: 26 out of 86 30%`
456			`IOB Flip Flops: 9`
457			`Number of GCLKs: 2 out of 4 50%`
458			`Number of GCLKIOBs: 2 out of 4 50%`
459			`Total equivalent gate count for design: 1,329`
460			`Additional JTAG gate count for IOBs: 1,344`
461
462			`Mapping completed.`
463			`See MAP report file "uart.mrp" for details.`
464			`Tcl e:/ise/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.`
465
466			`Done: completed successfully.`
467
468			`Starting: 'exewrap @_nc1TOncd_exewrap.rsp'`
469
470
471			`Creating TCL Process`
472			`Found _prepar.rsp`
473			`Starting: 'par -f _par.rsp'`
474
475
476			`Release 4.2i - Par E.35`
477			`Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.`
478
479
480			`WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".`
481
482
483			`Constraints file: uart.pcf`
484
485			`Loading design for application par from file par_temp.ncd.`
486			`"uart" is an NCD, version 2.37, device xc2s15, package cs144, speed -6`
487			`Loading device for application par from file '2s15.nph' in environment e:/ise.`
488			`Device speed data version: PRELIMINARY 1.23 2001-12-19.`
489
490
491			`Resolving physical constraints.`
492			`Finished resolving physical constraints.`
493
494			`Device utilization summary:`
495
496			`Number of External GCLKIOBs 2 out of 4 50%`
497			`Number of External IOBs 26 out of 86 30%`
498			`Number of LOCed External IOBs 0 out of 26 0%`
499
500			`Number of SLICEs 83 out of 192 43%`
501
502			`Number of GCLKs 2 out of 4 50%`
503
504
505
506			`Overall effort level (-ol): 2 (set by user)`
507			`Placer effort level (-pl): 2 (set by user)`
508			`Placer cost table entry (-t): 1`
509			`Router effort level (-rl): 2 (set by user)`
510			`Extra effort level (-xe): 0 (set by user)`
511
512			`Starting initial Placement phase. REAL time: 0 secs`
513			`Finished initial Placement phase. REAL time: 0 secs`
514			`Starting the placer. REAL time: 0 secs`
515			`Placement pass 1 ....`
516			`Placer score = 7875`
517			`Placement pass 2 ...............`
518			`Placer score = 7375`
519			`Optimizing ...`
520			`Placer score = 6385`
521			`Placer score = 5890`
522			`Placer completed in real time: 0 secs`
523
524			`Dumping design to file uart.ncd.`
525
526			`Total REAL time to Placer completion: 0 secs`
527			`Total CPU time to Placer completion: 1 secs`
528
529
530			`Starting router resource preassignment`
531			`Completed router resource preassignment. REAL time: 0 secs`
532			`Starting iterative routing.`
533			`Routing active signals.`
534			`.....`
535			`End of iteration 1`
536			`526 successful; 0 unrouted; (0) REAL time: 0 secs`
537			`Constraints are met.`
538			`Total REAL time: 2 secs`
539			`Total CPU time: 1 secs`
540			`End of route. 526 routed (100.00%); 0 unrouted.`
541			`No errors found.`
542			`Completely routed.`
543
544			`This design was run without timing constraints. It is likely that much better`
545			`circuit performance can be obtained by trying either or both of the following:`
546
547			`- Enabling the Delay Based Cleanup router pass, if not already enabled`
548			`- Supplying timing constraints in the input design`
549
550
551			`Total REAL time to Router completion: 2 secs`
552			`Total CPU time to Router completion: 1 secs`
553
554			`Generating PAR statistics.`
555			`Dumping design to file uart.ncd.`
556
557
558			`All signals are completely routed.`
559
560			`Total REAL time to PAR completion: 4 secs`
561			`Total CPU time to PAR completion: 1 secs`
562
563			`Placement: Completed - No errors found.`
564			`Routing: Completed - No errors found.`
565
566			`PAR done.`
567			`Tcl e:/ise/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.`
568
569			`PAR completed successfully`
570			`Done: completed successfully.`
571
572			`Launching: 'exewrap -tcl -command __launchTA.tcl'`
573
574
575
576			`ISE Auto-Make Log File`
577			`-----------------------`
578
579			`Starting: 'jhdparse @Rxunit.jp'`
580
581
582			`JHDPARSE - VHDL/Verilog Parser.`
583			`ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.`
584
585			`Scanning j:/rtl/vhdl/Rxunit.vhd`
586			`Scanning j:/rtl/vhdl/Rxunit.vhd`
587			`Writing Rxunit.jhd.`
588
589			`JHDPARSE complete - 0 errors, 0 warnings.`
590
591			`Done: completed successfully.`
592
593			`Starting: 'jhdparse @Txunit.jp'`
594
595
596
597			`Starting: 'jhdparse @utils.jp'`
598
599
600			`JHDPARSE - VHDL/Verilog Parser.`
601			`ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.`
602
603			`Scanning j:/rtl/vhdl/utils.vhd`
604			`Scanning j:/rtl/vhdl/utils.vhd`
605			`j:/rtl/vhdl/utils.vhd(47) library IEEE,STD;`
606			`^`
607			`Warning 0008: Unable to open library std.`
608			`Writing utils.jhd.`
609
610			`JHDPARSE complete - 0 errors, 1 warning.`
611
612			`Done: completed successfully.`
613
614			`Starting: 'jhdparse @miniuart.jp'`
615
616
617