1 |
22 |
philippe |
Release 4.2i - Map E.35
|
2 |
|
|
Xilinx Mapping Report File for Design 'uart'
|
3 |
|
|
|
4 |
|
|
Design Information
|
5 |
|
|
------------------
|
6 |
|
|
Command Line : map -p xc2s15-cs144-6 -cm area -k 4 -c 100 -tx off uart.ngd
|
7 |
|
|
Target Device : x2s15
|
8 |
|
|
Target Package : cs144
|
9 |
|
|
Target Speed : -6
|
10 |
|
|
Mapper Version : spartan2 -- $Revision: 1.1.1.1 $
|
11 |
|
|
Mapped Date : Thu Jan 09 18:11:05 2003
|
12 |
|
|
|
13 |
|
|
Design Summary
|
14 |
|
|
--------------
|
15 |
|
|
Number of errors: 0
|
16 |
|
|
Number of warnings: 0
|
17 |
|
|
Number of Slices: 83 out of 192 43%
|
18 |
|
|
Number of Slices containing
|
19 |
|
|
unrelated logic: 0 out of 83 0%
|
20 |
|
|
Number of Slice Flip Flops: 63 out of 384 16%
|
21 |
|
|
Total Number 4 input LUTs: 115 out of 384 29%
|
22 |
|
|
Number used as LUTs: 110
|
23 |
|
|
Number used as a route-thru: 5
|
24 |
|
|
Number of bonded IOBs: 26 out of 86 30%
|
25 |
|
|
IOB Flip Flops: 9
|
26 |
|
|
Number of GCLKs: 2 out of 4 50%
|
27 |
|
|
Number of GCLKIOBs: 2 out of 4 50%
|
28 |
|
|
Total equivalent gate count for design: 1,329
|
29 |
|
|
Additional JTAG gate count for IOBs: 1,344
|
30 |
|
|
|
31 |
|
|
Table of Contents
|
32 |
|
|
-----------------
|
33 |
|
|
Section 1 - Errors
|
34 |
|
|
Section 2 - Warnings
|
35 |
|
|
Section 3 - Informational
|
36 |
|
|
Section 4 - Removed Logic Summary
|
37 |
|
|
Section 5 - Removed Logic
|
38 |
|
|
Section 6 - IOB Properties
|
39 |
|
|
Section 7 - RPMs
|
40 |
|
|
Section 8 - Guide Report
|
41 |
|
|
Section 9 - Area Group Summary
|
42 |
|
|
Section 10 - Modular Design Summary
|
43 |
|
|
|
44 |
|
|
Section 1 - Errors
|
45 |
|
|
------------------
|
46 |
|
|
|
47 |
|
|
Section 2 - Warnings
|
48 |
|
|
--------------------
|
49 |
|
|
|
50 |
|
|
Section 3 - Informational
|
51 |
|
|
-------------------------
|
52 |
|
|
INFO:MapLib:62 - All of the external outputs in this design are using slew rate
|
53 |
|
|
limited output drivers. The delay on speed critical outputs can be
|
54 |
|
|
dramatically reduced by designating them as fast outputs in the schematic.
|
55 |
|
|
|
56 |
|
|
Section 4 - Removed Logic Summary
|
57 |
|
|
---------------------------------
|
58 |
|
|
2 block(s) optimized away
|
59 |
|
|
|
60 |
|
|
Section 5 - Removed Logic
|
61 |
|
|
-------------------------
|
62 |
|
|
|
63 |
|
|
Optimized Block(s):
|
64 |
|
|
TYPE BLOCK
|
65 |
|
|
GND GND_I
|
66 |
|
|
VCC VCC_I
|
67 |
|
|
|
68 |
|
|
To enable printing of redundant blocks removed and signals merged, set the
|
69 |
|
|
detailed map report option and rerun map.
|
70 |
|
|
|
71 |
|
|
Section 6 - IOB Properties
|
72 |
|
|
--------------------------
|
73 |
|
|
|
74 |
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
75 |
|
|
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
|
76 |
|
|
| | | | | Strength | Rate | | | Delay |
|
77 |
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
78 |
|
|
| br_clk_i | GCLKIOB | INPUT | LVTTL | | | | | |
|
79 |
|
|
| wb_clk_i | GCLKIOB | INPUT | LVTTL | | | | | |
|
80 |
|
|
| intrx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | |
|
81 |
|
|
| inttx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
82 |
|
|
| rxd_pad_i | IOB | INPUT | LVTTL | | | | | |
|
83 |
|
|
| txd_pad_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
84 |
|
|
| wb_ack_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
85 |
|
|
| wb_adr_i<0> | IOB | INPUT | LVTTL | | | | | |
|
86 |
|
|
| wb_adr_i<1> | IOB | INPUT | LVTTL | | | | | |
|
87 |
|
|
| wb_dat_i<0> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
88 |
|
|
| wb_dat_i<1> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
89 |
|
|
| wb_dat_i<2> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
90 |
|
|
| wb_dat_i<3> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
91 |
|
|
| wb_dat_i<4> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
92 |
|
|
| wb_dat_i<5> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
93 |
|
|
| wb_dat_i<6> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
94 |
|
|
| wb_dat_i<7> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
|
95 |
|
|
| wb_dat_o<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
96 |
|
|
| wb_dat_o<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
97 |
|
|
| wb_dat_o<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
98 |
|
|
| wb_dat_o<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
99 |
|
|
| wb_dat_o<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
100 |
|
|
| wb_dat_o<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
101 |
|
|
| wb_dat_o<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
102 |
|
|
| wb_dat_o<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
103 |
|
|
| wb_rst_i | IOB | INPUT | LVTTL | | | | | |
|
104 |
|
|
| wb_stb_i | IOB | INPUT | LVTTL | | | | | |
|
105 |
|
|
| wb_we_i | IOB | INPUT | LVTTL | | | | | |
|
106 |
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
107 |
|
|
|
108 |
|
|
Section 7 - RPMs
|
109 |
|
|
----------------
|
110 |
|
|
|
111 |
|
|
Section 8 - Guide Report
|
112 |
|
|
------------------------
|
113 |
|
|
Guide not run on this design.
|
114 |
|
|
|
115 |
|
|
Section 9 - Area Group Summary
|
116 |
|
|
------------------------------
|
117 |
|
|
No area groups were found in this design.
|
118 |
|
|
|
119 |
|
|
Section 10 - Modular Design Summary
|
120 |
|
|
-----------------------------------
|
121 |
|
|
Modular Design not used for this design.
|