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philippe |
Release 4.2i - Map E.35
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Xilinx Mapping Report File for Design 'uart'
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Design Information
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------------------
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Command Line : map -p xc2s15-cs144-6 -cm area -k 4 -c 100 -tx off uart.ngd
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Target Device : x2s15
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Target Package : cs144
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Target Speed : -6
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Mapper Version : spartan2 -- $Revision: 1.1.1.1 $
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Mapped Date : Thu Jan 09 18:11:05 2003
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 0
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Number of Slices: 83 out of 192 43%
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Number of Slices containing
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unrelated logic: 0 out of 83 0%
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Number of Slice Flip Flops: 63 out of 384 16%
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Total Number 4 input LUTs: 115 out of 384 29%
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Number used as LUTs: 110
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Number used as a route-thru: 5
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Number of bonded IOBs: 26 out of 86 30%
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IOB Flip Flops: 9
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Number of GCLKs: 2 out of 4 50%
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Number of GCLKIOBs: 2 out of 4 50%
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Total equivalent gate count for design: 1,329
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Additional JTAG gate count for IOBs: 1,344
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group Summary
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Section 10 - Modular Design Summary
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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Section 3 - Informational
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-------------------------
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INFO:MapLib:62 - All of the external outputs in this design are using slew rate
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limited output drivers. The delay on speed critical outputs can be
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dramatically reduced by designating them as fast outputs in the schematic.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE BLOCK
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GND GND_I
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VCC VCC_I
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Strength | Rate | | | Delay |
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+------------------------------------------------------------------------------------------------------------------------+
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| br_clk_i | GCLKIOB | INPUT | LVTTL | | | | | |
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| wb_clk_i | GCLKIOB | INPUT | LVTTL | | | | | |
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| intrx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | |
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| inttx_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| rxd_pad_i | IOB | INPUT | LVTTL | | | | | |
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| txd_pad_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_ack_o | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_adr_i<0> | IOB | INPUT | LVTTL | | | | | |
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| wb_adr_i<1> | IOB | INPUT | LVTTL | | | | | |
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| wb_dat_i<0> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<1> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<2> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<3> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<4> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<5> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<6> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_i<7> | IOB | INPUT | LVTTL | | | INFF | | DELAY |
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| wb_dat_o<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_dat_o<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| wb_rst_i | IOB | INPUT | LVTTL | | | | | |
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| wb_stb_i | IOB | INPUT | LVTTL | | | | | |
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| wb_we_i | IOB | INPUT | LVTTL | | | | | |
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+------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group Summary
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------------------------------
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No area groups were found in this design.
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Section 10 - Modular Design Summary
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-----------------------------------
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Modular Design not used for this design.
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