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philippe |
Release 4.2i - Par E.35
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Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
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Thu Jan 09 18:11:08 2003
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par -f _par.rsp
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Constraints file: uart.pcf
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Loading design for application par from file par_temp.ncd.
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"uart" is an NCD, version 2.37, device xc2s15, package cs144, speed -6
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Loading device for application par from file '2s15.nph' in environment e:/ise.
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Device speed data version: PRELIMINARY 1.23 2001-12-19.
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Device utilization summary:
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Number of External GCLKIOBs 2 out of 4 50%
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Number of External IOBs 26 out of 86 30%
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Number of LOCed External IOBs 0 out of 26 0%
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Number of SLICEs 83 out of 192 43%
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Number of GCLKs 2 out of 4 50%
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Overall effort level (-ol): 2 (set by user)
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Placer effort level (-pl): 2 (set by user)
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Placer cost table entry (-t): 1
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Router effort level (-rl): 2 (set by user)
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Extra effort level (-xe): 0 (set by user)
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Starting initial Placement phase. REAL time: 0 secs
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Finished initial Placement phase. REAL time: 0 secs
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Starting the placer. REAL time: 0 secs
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Placement pass 1 ....
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Placer score = 7875
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Placement pass 2 ...............
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Placer score = 7375
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Optimizing ...
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Placer score = 6385
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Placer score = 5890
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Placer completed in real time: 0 secs
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Dumping design to file uart.ncd.
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Total REAL time to Placer completion: 0 secs
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Total CPU time to Placer completion: 1 secs
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Starting router resource preassignment
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Completed router resource preassignment. REAL time: 0 secs
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Starting iterative routing.
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Routing active signals.
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.....
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End of iteration 1
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526 successful; 0 unrouted; (0) REAL time: 0 secs
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Constraints are met.
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Total REAL time: 2 secs
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Total CPU time: 1 secs
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End of route. 526 routed (100.00%); 0 unrouted.
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No errors found.
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Completely routed.
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This design was run without timing constraints. It is likely that much better
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circuit performance can be obtained by trying either or both of the following:
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- Enabling the Delay Based Cleanup router pass, if not already enabled
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- Supplying timing constraints in the input design
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Total REAL time to Router completion: 2 secs
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Total CPU time to Router completion: 1 secs
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Generating PAR statistics.
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The Delay Summary Report
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The Score for this design is: 132
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The Number of signals not completely routed for this design is: 0
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The Average Connection Delay for this design is: 1.010 ns
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The Maximum Pin Delay is: 2.509 ns
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The Average Connection Delay on the 10 Worst Nets is: 1.597 ns
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Listing Pin Delays by value: (ns)
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d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
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--------- --------- --------- --------- --------- ---------
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258 259 9 0 0 0
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Dumping design to file uart.ncd.
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All signals are completely routed.
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Total REAL time to PAR completion: 4 secs
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Total CPU time to PAR completion: 1 secs
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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PAR done.
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