URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [uart.syr] - Blame information for rev 26

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Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VHDL
Input File Name                    : uart.prj
 
---- Target Parameters
Target Device                      : xc2s15-cs144-6
Output File Name                   : uart
Output Format                      : NGC
Target Technology                  : spartan2
 
---- Source Options
Entity Name                        : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6
 
---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
 
=========================================================================
 
Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work.
Entity  (Architecture ) compiled.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work.
Entity  (Architecture ) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work.
Entity  (Architecture ) compiled.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing generic Entity  (Architecture ).
        count = 130
Entity  analyzed. Unit  generated.
 
Analyzing generic Entity  (Architecture ).
        count = 4
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing Entity  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred   3 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd.
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 2-bit adder for signal <$n0002> created at line 91.
    Found 4-bit adder for signal <$n0018> created at line 85.
    Found 4-bit comparator greatequal for signal <$n0038> created at line 81.
    Found 4-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 2-bit register for signal .
    Summary:
        inferred  24 D-type flip-flop(s).
        inferred   2 Adder/Subtracter(s).
        inferred   1 Comparator(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/Txunit.vhd.
    Found 1-bit register for signal .
    Found 4-bit adder for signal <$n0012> created at line 92.
    Found 4-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtracter(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 2-bit down counter for signal .
WARNING:Xst:647 - Input  is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal .
    Found 8-bit down counter for signal .
WARNING:Xst:647 - Input  is never used.
WARNING:Xst:647 - Input  is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is J:/impl/../rtl/vhdl/miniuart.vhd.
WARNING:Xst:646 - Signal  is assigned but never used.
WARNING:Xst:646 - Signal  is assigned but never used.
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Summary:
        inferred  10 D-type flip-flop(s).
Unit  synthesized.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Registers                        : 26
  4-bit register                   : 2
  2-bit register                   : 1
  8-bit register                   : 4
  1-bit register                   : 19
# Counters                         : 2
  2-bit down counter               : 1
  8-bit down counter               : 1
# Adders/Subtractors               : 3
  2-bit adder                      : 1
  4-bit adder                      : 2
# Comparators                      : 1
  4-bit comparator greatequal      : 1
 
=========================================================================
 
 
Starting low level synthesis...
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Optimizing unit  ...
 
Building and optimizing final netlist ...
 
FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute.
=========================================================================
Final Results
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+
 
Macro Statistics
# Registers                        : 35
  4-bit register                   : 2
  8-bit register                   : 4
  2-bit register                   : 2
  1-bit register                   : 27
# Adders/Subtractors               : 3
  4-bit adder                      : 2
  8-bit subtractor                 : 1
 
Design Statistics
# IOs                              : 28
 
Cell Usage :
# BELS                             : 153
#      GND                         : 1
#      LUT1                        : 13
#      LUT1_D                      : 2
#      LUT1_L                      : 3
#      LUT2                        : 21
#      LUT3                        : 24
#      LUT3_L                      : 2
#      LUT4                        : 51
#      LUT4_D                      : 2
#      LUT4_L                      : 2
#      MUXCY                       : 13
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 14
# FlipFlops/Latches                : 72
#      FDC                         : 4
#      FDCE                        : 10
#      FDE                         : 40
#      FDPE                        : 1
#      FDR                         : 11
#      FDRE                        : 2
#      FDS                         : 2
#      FDSE                        : 2
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 26
#      IBUF                        : 14
#      OBUF                        : 12
=========================================================================
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
uart_rxunit_rregl:Q                | NONE                   | 3     |
br_clk_i                           | BUFGP                  | 59    |
loada:Q                            | NONE                   | 1     |
wb_clk_i                           | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -6
 
   Minimum period: 9.318ns (Maximum Frequency: 107.319MHz)
   Minimum input arrival time before clock: 8.430ns
   Maximum output required time after clock: 10.658ns
   Maximum combinational path delay: 9.098ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'br_clk_i'
Delay:               9.318ns (Levels of Logic = 6)
  Source:            uart_rxunit_bitpos_0
  Destination:       uart_rxunit_bitpos_2
  Source Clock:      br_clk_i rising
  Destination Clock: br_clk_i rising
 
  Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q             22   1.085   2.970  uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0)
    LUT1_D:I0->LO          1   0.549   0.000  uart_rxunit_Madd__n0018_inst_lut2_0 (N3009)
    MUXCY:S->O             1   0.659   0.000  uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0)
    MUXCY:CI->O            1   0.042   0.000  uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1)
    XORCY:CI->O            1   0.420   1.035  uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181)
    LUT4:I3->O             1   0.549   1.035  uart_rxunit_I_10_LUT_53 (uart_rxunit_N183)
    LUT4_L:I0->LO          1   0.549   0.000  uart_rxunit_I__n0005_2 (uart_rxunit_N201)
    FDCE:D                     0.425          uart_rxunit_bitpos_2
    ----------------------------------------
    Total                      9.318ns (4.278ns logic, 5.040ns route)
                                       (45.9% logic, 54.1% route)
 
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i'
Offset:              8.430ns (Levels of Logic = 3)
  Source:            wb_rst_i
  Destination:       uart_txunit_treg_5
  Destination Clock: br_clk_i rising
 
  Data Path: wb_rst_i to uart_txunit_treg_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             19   0.776   2.790  wb_rst_i_IBUF (wb_rst_i_IBUF)
    LUT4:I3->O             1   0.549   1.035  uart_txunit_I_1_LUT_11 (N2973)
    LUT4:I3->O             8   0.549   1.845  uart_txunit_I__n0009 (uart_txunit_N83)
    FDE:CE                     0.886          uart_txunit_treg_5
    ----------------------------------------
    Total                      8.430ns (2.760ns logic, 5.670ns route)
                                       (32.7% logic, 67.3% route)
 
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i'
Offset:              10.658ns (Levels of Logic = 3)
  Source:            uart_txunit_tbufl
  Destination:       wb_dat_o_0
  Source Clock:      br_clk_i rising
 
  Data Path: uart_txunit_tbufl to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q              5   1.085   1.566  uart_txunit_tbufl (uart_txunit_tbufl)
    LUT2:I1->O             2   0.549   1.206  uart_txunit_I_busy (N64)
    LUT4:I2->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                     10.658ns (6.851ns logic, 3.807ns route)
                                       (64.3% logic, 35.7% route)
 
-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.098ns (Levels of Logic = 3)
  Source:            wb_adr_i_1
  Destination:       wb_dat_o_0
 
  Data Path: wb_adr_i_1 to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             11   0.776   2.070  wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)
    LUT4:I0->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                      9.098ns (5.993ns logic, 3.105ns route)
                                       (65.9% logic, 34.1% route)
 
=========================================================================
CPU : 9.22 / 9.67 s | Elapsed : 10.00 / 10.00 s
 
-->

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Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [uart.syr] - Blame information for rev 26

Line No.	Rev	Author	Line
1	22	philippe	`Release 4.2i - xst E.35`
2			`Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.`
3			`--> Parameter TMPDIR set to .`
4			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
5
6			`--> Parameter overwrite set to YES`
7			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
8
9			`--> Parameter xsthdpdir set to ./xst`
10			`CPU : 0.00 / 0.45 s \| Elapsed : 0.00 / 0.00 s`
11
12			`--> =========================================================================`
13			`---- Source Parameters`
14			`Input Format : VHDL`
15			`Input File Name : uart.prj`
16
17			`---- Target Parameters`
18			`Target Device : xc2s15-cs144-6`
19			`Output File Name : uart`
20			`Output Format : NGC`
21			`Target Technology : spartan2`
22
23			`---- Source Options`
24			`Entity Name : uart`
25			`Automatic FSM Extraction : YES`
26			`FSM Encoding Algorithm : Auto`
27			`FSM Flip-Flop Type : D`
28			`Mux Extraction : YES`
29			`Resource Sharing : YES`
30			`Complex Clock Enable Extraction : YES`
31			`ROM Extraction : Yes`
32			`RAM Extraction : Yes`
33			`RAM Style : Auto`
34			`Mux Style : Auto`
35			`Decoder Extraction : YES`
36			`Priority Encoder Extraction : YES`
37			`Shift Register Extraction : YES`
38			`Logical Shifter Extraction : YES`
39			`XOR Collapsing : YES`
40			`Automatic Register Balancing : No`
41
42			`---- Target Options`
43			`Add IO Buffers : YES`
44			`Equivalent register Removal : YES`
45			`Add Generic Clock Buffer(BUFG) : 4`
46			`Global Maximum Fanout : 100`
47			`Register Duplication : YES`
48			`Move First FlipFlop Stage : YES`
49			`Move Last FlipFlop Stage : YES`
50			`Slice Packing : YES`
51			`Pack IO Registers into IOBs : auto`
52			`Speed Grade : 6`
53
54			`---- General Options`
55			`Optimization Criterion : Speed`
56			`Optimization Effort : 1`
57			`Check Attribute Syntax : YES`
58			`Keep Hierarchy : No`
59			`Global Optimization : AllClockNets`
60			`Write Timing Constraints : No`
61
62			`=========================================================================`
63
64			`Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work.`
65			`Entity (Architecture ) compiled.`
66			`Entity (Architecture ) compiled.`
67			`Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work.`
68			`Entity (Architecture ) compiled.`
69			`Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work.`
70			`Entity (Architecture ) compiled.`
71			`Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work.`
72			`Entity (Architecture ) compiled.`
73
74			`Analyzing Entity (Architecture ).`
75			`Entity analyzed. Unit generated.`
76
77			`Analyzing generic Entity (Architecture ).`
78			`count = 130`
79			`Entity analyzed. Unit generated.`
80
81			`Analyzing generic Entity (Architecture ).`
82			`count = 4`
83			`Entity analyzed. Unit generated.`
84
85			`Analyzing Entity (Architecture ).`
86			`Entity analyzed. Unit generated.`
87
88			`Analyzing Entity (Architecture ).`
89			`Entity analyzed. Unit generated.`
90
91			`Analyzing Entity (Architecture ).`
92			`Entity analyzed. Unit generated.`
93
94
95			`Synthesizing Unit .`
96			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
97			`Found 1-bit register for signal .`
98			`Found 1-bit register for signal .`
99			`Found 1-bit register for signal .`
100			`Summary:`
101			`inferred 3 D-type flip-flop(s).`
102			`Unit synthesized.`
103
104
105			`Synthesizing Unit .`
106			`Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd.`
107			`Found 1-bit register for signal .`
108			`Found 8-bit register for signal .`
109			`Found 2-bit adder for signal <$n0002> created at line 91.`
110			`Found 4-bit adder for signal <$n0018> created at line 85.`
111			`Found 4-bit comparator greatequal for signal <$n0038> created at line 81.`
112			`Found 4-bit register for signal .`
113			`Found 8-bit register for signal .`
114			`Found 1-bit register for signal .`
115			`Found 2-bit register for signal .`
116			`Summary:`
117			`inferred 24 D-type flip-flop(s).`
118			`inferred 2 Adder/Subtracter(s).`
119			`inferred 1 Comparator(s).`
120			`Unit synthesized.`
121
122
123			`Synthesizing Unit .`
124			`Related source file is J:/impl/../rtl/vhdl/Txunit.vhd.`
125			`Found 1-bit register for signal .`
126			`Found 4-bit adder for signal <$n0012> created at line 92.`
127			`Found 4-bit register for signal .`
128			`Found 8-bit register for signal .`
129			`Found 1-bit register for signal .`
130			`Found 8-bit register for signal .`
131			`Summary:`
132			`inferred 22 D-type flip-flop(s).`
133			`inferred 1 Adder/Subtracter(s).`
134			`Unit synthesized.`
135
136
137			`Synthesizing Unit .`
138			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
139			`Found 1-bit register for signal .`
140			`Found 2-bit down counter for signal .`
141			`WARNING:Xst:647 - Input is never used.`
142			`Summary:`
143			`inferred 1 Counter(s).`
144			`inferred 1 D-type flip-flop(s).`
145			`Unit synthesized.`
146
147
148			`Synthesizing Unit .`
149			`Related source file is J:/impl/../rtl/vhdl/utils.vhd.`
150			`Found 1-bit register for signal .`
151			`Found 8-bit down counter for signal .`
152			`WARNING:Xst:647 - Input is never used.`
153			`WARNING:Xst:647 - Input is never used.`
154			`Summary:`
155			`inferred 1 Counter(s).`
156			`inferred 1 D-type flip-flop(s).`
157			`Unit synthesized.`
158
159
160			`Synthesizing Unit .`
161			`Related source file is J:/impl/../rtl/vhdl/miniuart.vhd.`
162			`WARNING:Xst:646 - Signal is assigned but never used.`
163			`WARNING:Xst:646 - Signal is assigned but never used.`
164			`Found 1-bit register for signal .`
165			`Found 1-bit register for signal .`
166			`Found 8-bit register for signal .`
167			`Summary:`
168			`inferred 10 D-type flip-flop(s).`
169			`Unit synthesized.`
170
171			`=========================================================================`
172			`HDL Synthesis Report`
173
174			`Macro Statistics`
175			`# Registers : 26`
176			`4-bit register : 2`
177			`2-bit register : 1`
178			`8-bit register : 4`
179			`1-bit register : 19`
180			`# Counters : 2`
181			`2-bit down counter : 1`
182			`8-bit down counter : 1`
183			`# Adders/Subtractors : 3`
184			`2-bit adder : 1`
185			`4-bit adder : 2`
186			`# Comparators : 1`
187			`4-bit comparator greatequal : 1`
188
189			`=========================================================================`
190
191
192			`Starting low level synthesis...`
193			`Optimizing unit ...`
194
195			`Optimizing unit ...`
196
197			`Optimizing unit ...`
198
199			`Optimizing unit ...`
200
201			`Building and optimizing final netlist ...`
202
203			`FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute.`
204			`=========================================================================`
205			`Final Results`
206			`Top Level Output File Name : uart`
207			`Output Format : NGC`
208			`Optimization Criterion : Speed`
209			`Target Technology : spartan2`
210			`Keep Hierarchy : No`
211			`Macro Generator : macro+`
212
213			`Macro Statistics`
214			`# Registers : 35`
215			`4-bit register : 2`
216			`8-bit register : 4`
217			`2-bit register : 2`
218			`1-bit register : 27`
219			`# Adders/Subtractors : 3`
220			`4-bit adder : 2`
221			`8-bit subtractor : 1`
222
223			`Design Statistics`
224			`# IOs : 28`
225
226			`Cell Usage :`
227			`# BELS : 153`
228			`# GND : 1`
229			`# LUT1 : 13`
230			`# LUT1_D : 2`
231			`# LUT1_L : 3`
232			`# LUT2 : 21`
233			`# LUT3 : 24`
234			`# LUT3_L : 2`
235			`# LUT4 : 51`
236			`# LUT4_D : 2`
237			`# LUT4_L : 2`
238			`# MUXCY : 13`
239			`# MUXF5 : 4`
240			`# VCC : 1`
241			`# XORCY : 14`
242			`# FlipFlops/Latches : 72`
243			`# FDC : 4`
244			`# FDCE : 10`
245			`# FDE : 40`
246			`# FDPE : 1`
247			`# FDR : 11`
248			`# FDRE : 2`
249			`# FDS : 2`
250			`# FDSE : 2`
251			`# Clock Buffers : 2`
252			`# BUFGP : 2`
253			`# IO Buffers : 26`
254			`# IBUF : 14`
255			`# OBUF : 12`
256			`=========================================================================`
257
258
259			`=========================================================================`
260			`TIMING REPORT`
261
262			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
263			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
264			`GENERATED AFTER PLACE-and-ROUTE.`
265
266			`Clock Information:`
267			`------------------`
268			`-----------------------------------+------------------------+-------+`
269			`Clock Signal \| Clock buffer(FF name) \| Load \|`
270			`-----------------------------------+------------------------+-------+`
271			`uart_rxunit_rregl:Q \| NONE \| 3 \|`
272			`br_clk_i \| BUFGP \| 59 \|`
273			`loada:Q \| NONE \| 1 \|`
274			`wb_clk_i \| BUFGP \| 10 \|`
275			`-----------------------------------+------------------------+-------+`
276
277			`Timing Summary:`
278			`---------------`
279			`Speed Grade: -6`
280
281			`Minimum period: 9.318ns (Maximum Frequency: 107.319MHz)`
282			`Minimum input arrival time before clock: 8.430ns`
283			`Maximum output required time after clock: 10.658ns`
284			`Maximum combinational path delay: 9.098ns`
285
286			`Timing Detail:`
287			`--------------`
288			`All values displayed in nanoseconds (ns)`
289
290			`-------------------------------------------------------------------------`
291			`Timing constraint: Default period analysis for Clock 'br_clk_i'`
292			`Delay: 9.318ns (Levels of Logic = 6)`
293			`Source: uart_rxunit_bitpos_0`
294			`Destination: uart_rxunit_bitpos_2`
295			`Source Clock: br_clk_i rising`
296			`Destination Clock: br_clk_i rising`
297
298			`Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2`
299			`Gate Net`
300			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
301			`---------------------------------------- ------------`
302			`FDCE:C->Q 22 1.085 2.970 uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0)`
303			`LUT1_D:I0->LO 1 0.549 0.000 uart_rxunit_Madd__n0018_inst_lut2_0 (N3009)`
304			`MUXCY:S->O 1 0.659 0.000 uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0)`
305			`MUXCY:CI->O 1 0.042 0.000 uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1)`
306			`XORCY:CI->O 1 0.420 1.035 uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181)`
307			`LUT4:I3->O 1 0.549 1.035 uart_rxunit_I_10_LUT_53 (uart_rxunit_N183)`
308			`LUT4_L:I0->LO 1 0.549 0.000 uart_rxunit_I__n0005_2 (uart_rxunit_N201)`
309			`FDCE:D 0.425 uart_rxunit_bitpos_2`
310			`----------------------------------------`
311			`Total 9.318ns (4.278ns logic, 5.040ns route)`
312			`(45.9% logic, 54.1% route)`
313
314			`-------------------------------------------------------------------------`
315			`Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i'`
316			`Offset: 8.430ns (Levels of Logic = 3)`
317			`Source: wb_rst_i`
318			`Destination: uart_txunit_treg_5`
319			`Destination Clock: br_clk_i rising`
320
321			`Data Path: wb_rst_i to uart_txunit_treg_5`
322			`Gate Net`
323			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
324			`---------------------------------------- ------------`
325			`IBUF:I->O 19 0.776 2.790 wb_rst_i_IBUF (wb_rst_i_IBUF)`
326			`LUT4:I3->O 1 0.549 1.035 uart_txunit_I_1_LUT_11 (N2973)`
327			`LUT4:I3->O 8 0.549 1.845 uart_txunit_I__n0009 (uart_txunit_N83)`
328			`FDE:CE 0.886 uart_txunit_treg_5`
329			`----------------------------------------`
330			`Total 8.430ns (2.760ns logic, 5.670ns route)`
331			`(32.7% logic, 67.3% route)`
332
333			`-------------------------------------------------------------------------`
334			`Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i'`
335			`Offset: 10.658ns (Levels of Logic = 3)`
336			`Source: uart_txunit_tbufl`
337			`Destination: wb_dat_o_0`
338			`Source Clock: br_clk_i rising`
339
340			`Data Path: uart_txunit_tbufl to wb_dat_o_0`
341			`Gate Net`
342			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
343			`---------------------------------------- ------------`
344			`FDCE:C->Q 5 1.085 1.566 uart_txunit_tbufl (uart_txunit_tbufl)`
345			`LUT2:I1->O 2 0.549 1.206 uart_txunit_I_busy (N64)`
346			`LUT4:I2->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF)`
347			`OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0)`
348			`----------------------------------------`
349			`Total 10.658ns (6.851ns logic, 3.807ns route)`
350			`(64.3% logic, 35.7% route)`
351
352			`-------------------------------------------------------------------------`
353			`Timing constraint: Default path analysis`
354			`Delay: 9.098ns (Levels of Logic = 3)`
355			`Source: wb_adr_i_1`
356			`Destination: wb_dat_o_0`
357
358			`Data Path: wb_adr_i_1 to wb_dat_o_0`
359			`Gate Net`
360			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
361			`---------------------------------------- ------------`
362			`IBUF:I->O 11 0.776 2.070 wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)`
363			`LUT4:I0->O 1 0.549 1.035 I_wb_dat_o_0 (wb_dat_o_0_OBUF)`
364			`OBUF:I->O 4.668 wb_dat_o_0_OBUF (wb_dat_o_0)`
365			`----------------------------------------`
366			`Total 9.098ns (5.993ns logic, 3.105ns route)`
367			`(65.9% logic, 34.1% route)`
368
369			`=========================================================================`
370			`CPU : 9.22 / 9.67 s \| Elapsed : 10.00 / 10.00 s`
371
372			`-->`