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[/] [miniuart2/] [trunk/] [rtl/] [vhdl/] [utils.vhd] - Blame information for rev 29

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-------------------------------------------------------------------------------
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-- Title      : UART
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-- Project    : UART
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-------------------------------------------------------------------------------
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-- File        : utils.vhd
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-- Author      : Philippe CARTON
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--               (philippe.carton2@libertysurf.fr)
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-- Organization:
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-- Created     : 15/12/2001
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-- Last update : 8/1/2003
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-- Platform    : Foundation 3.1i
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-- Simulators  : ModelSim 5.5b
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-- Synthesizers: Xilinx Synthesis
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-- Targets     : Xilinx Spartan
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-- Dependency  : IEEE std_logic_1164
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-------------------------------------------------------------------------------
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-- Description: VHDL utility file
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-------------------------------------------------------------------------------
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-- Copyright (c) notice
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--    This core adheres to the GNU public license
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--
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-------------------------------------------------------------------------------
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-- Revisions       :
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-- Revision Number :
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-- Version         :
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-- Date    :
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-- Modifier        : name <email>
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-- Description     :
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--
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------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version   Author                 Date                        Changes
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--
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-- 1.0      Philippe CARTON  19 December 2001                   New model
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--          philippe.carton2@libertysurf.fr
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-------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Synchroniser:
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--    Synchronize an input signal (C1) with an input clock (C).
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--    The result is the O signal which is synchronous of C, and persist for
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--    one C clock period.
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--------------------------------------------------------------------------------
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library IEEE,STD;
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use IEEE.std_logic_1164.all;
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entity synchroniser is
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   port (
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      C1 : in std_logic;-- Asynchronous signal
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      C :  in std_logic;-- Clock
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      O :  out std_logic);-- Synchronised signal
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end synchroniser;
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architecture Behaviour of synchroniser is
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   signal C1A : std_logic;
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   signal C1S : std_logic;
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   signal R : std_logic;
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begin
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   RiseC1A : process(C1,R)
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   begin
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      if Rising_Edge(C1) then
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         C1A <= '1';
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      end if;
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      if (R = '1') then
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         C1A <= '0';
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      end if;
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   end process;
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   SyncP : process(C,R)
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   begin
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      if Rising_Edge(C) then
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         if (C1A = '1') then
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            C1S <= '1';
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         else C1S <= '0';
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         end if;
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         if (C1S = '1') then
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            R <= '1';
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         else R <= '0';
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         end if;
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      end if;
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      if (R = '1') then
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         C1S <= '0';
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      end if;
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   end process;
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   O <= C1S;
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end Behaviour;
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-------------------------------------------------------------------------------
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-- Counter
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--    This counter is a parametrizable clock divider.
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--    The count value is the generic parameter Count.
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--    It is CE enabled. (it will count only if CE is high).
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--    When it overflow, it will emit a pulse on O.
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--    It can be reseted to 0.
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-------------------------------------------------------------------------------
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library IEEE,STD;
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use IEEE.std_logic_1164.all;
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entity Counter is
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  generic(Count: INTEGER range 0 to 65535); -- Count revolution
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  port (
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     Clk      : in  std_logic;  -- Clock
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     Reset    : in  std_logic;  -- Reset input
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     CE       : in  std_logic;  -- Chip Enable
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     O        : out std_logic); -- Output
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end Counter;
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architecture Behaviour of Counter is
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begin
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  counter : process(Clk,Reset)
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     variable Cnt : INTEGER range 0 to Count-1;
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  begin
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     if Reset = '1' then
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        Cnt := Count - 1;
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        O <= '0';
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     elsif Rising_Edge(Clk) then
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        if CE = '1' then
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           if Cnt = 0 then
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              O <= '1';
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              Cnt := Count - 1;
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           else
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              O <= '0';
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              Cnt := Cnt - 1;
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           end if;
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        else O <= '0';
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        end if;
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     end if;
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  end process;
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end Behaviour;

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