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[/] [miniuart2/] [trunk/] [sim/] [Foundation sim/] [TESTTx.CMD] - Blame information for rev 26

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Line No. Rev Author Line
1 22 philippe
| Script file for testing the UART in echo mode (Txd and must be RxD tied)
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| 2 writes followed by 2 read
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| Initial settings
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delete_waveforms
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restart
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stepsize 50nS
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| Watched Signals and Vectors
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|
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| Define your signal and vector watch list here
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watch WB_CLK_I
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watch WB_RST_I
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watch WB_WE_I
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watch WB_STB_I
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watch WB_ACK_O
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vector WB_ADR WB_ADR_I[1:0]
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vector WB_DI WB_DAT_I[7:0]
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vector WB_DO WB_DAT_O[7:0]
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watch TxD_PAD_O | RS232 Tx Line
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watch IntTx_O   | Byte present in buffer
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watch IntRx_O   | Emit Buffer is empty
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watch BR_Clk_I
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watch EnabTx EnabRx
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| Stimulators Assignment
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| 1/Write Byte
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| 2/Write another byte
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clock WB_CLK_I  1 0
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wfm WB_RST_I    @1nS=L 100nS=H 100nS=L
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wfm WB_STB_I    @1nS=L +
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                        @100.001uS=H 100nS=L +
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                                @250.001uS=H 100nS=L
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wfm WB_WE_I             @1nS=L +
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                                @100.001uS=H +
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                                @250.001uS=H
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wfm WB_ADR              @1nS=L +
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                                @100.001uS=0\H 100nS=Z +
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                                @250.001uS=0\H 100nS=Z
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wfm WB_DI               @1nS=\0H +
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                                @100.001uS=81\H 101nS=Z +
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                                @250.001uS=55\H 101nS=Z
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wfm BR_Clk_I @610nS=L (500nS=H 500nS=L)*1500
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| Perform Simulation
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sim 1500uS
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