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[/] [miniuart2/] [trunk/] [sim/] [ModelSim/] [test_bench2/] [clk.in] - Blame information for rev 26

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Line No. Rev Author Line
1 22 philippe
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-- file clk.in
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--
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-- build a clock signal at 10MHz
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-- format :
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-- p -> period
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-- d -> delay / start. simu. > 0
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-- r -> cyclic ratio in %
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-- or
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-- h high state time
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-- c -> cycle number (~pattern number)
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----------------------
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p 100 ns
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d 1 ns
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r 50
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c 50000000
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--
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-- end of file

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