URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [sim/] [rtl_sim/] [bin/] [TESTUART.CMD] - Blame information for rev 26

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| Script file for testing the UART in echo mode (Txd and must be RxD tied)
| 2 writes followed by 2 read
 
| Initial settings
delete_waveforms
restart
stepsize 50nS
 
| Watched Signals and Vectors
|
| Define your signal and vector watch list here
watch WB_CLK_I
watch WB_RST_I
watch WB_WE_I
watch WB_STB_I
watch WB_ACK_O
vector WB_ADR ADR_I[1:0]
vector WB_DI DAT_I[7:0]
vector WB_DO DAT_O[7:0]
watch RxD       TEcho| RS232 Rx Line
watch TxD       | RS232 Tx Line
watch IntTx | Byte present in buffer
watch IntRx     | Emit Buffer is empty
watch BRClk
watch EnabTx EnabRx
 
| Stimulators Assignment
| 1/Write Byte
| 2/Write another byte
| 3/Read Byte
| 4/Read Byte
clock WB_CLK_I  1 0
wfm WB_RST_I    @1nS=L 100nS=H 100nS=L
wfm WB_STB_I    @1nS=L +
                        @100.001uS=H 100nS=L +
                                @200.001uS=H 100nS=L +
                                @250.001uS=H 100nS=L +
                                @355.501uS=H 100nS=L
wfm WB_WE_I             @1nS=L +
                                @100.001uS=H +
                    @200.001uS=L +
                                @250.001uS=H +
                    @355.501uS=L
wfm WB_ADR              @1nS=L +
                                @100.001uS=0\H 100nS=Z +
                                @200.001uS=0\H 100nS=Z +
                                @250.001uS=0\H 100nS=Z +
                    @355.501uS=0\H 100nS=Z
wfm WB_DI               @1nS=\0H +
                                @100.001uS=81\H 101nS=Z +
                                @250.001uS=55\H 101nS=Z
wfm BRClk @0nS=L (500nS=H 500nS=L)*500
 
| Perform Simulation
sim 400uS
 

Line No.	Rev	Author	Line
1	2	philippe	`\| Script file for testing the UART in echo mode (Txd and must be RxD tied)`
2			`\| 2 writes followed by 2 read`
3
4			`\| Initial settings`
5			`delete_waveforms`
6			`restart`
7			`stepsize 50nS`
8
9			`\| Watched Signals and Vectors`
10			`\|`
11			`\| Define your signal and vector watch list here`
12			`watch WB_CLK_I`
13			`watch WB_RST_I`
14			`watch WB_WE_I`
15			`watch WB_STB_I`
16			`watch WB_ACK_O`
17			`vector WB_ADR ADR_I[1:0]`
18			`vector WB_DI DAT_I[7:0]`
19			`vector WB_DO DAT_O[7:0]`
20			`watch RxD TEcho\| RS232 Rx Line`
21			`watch TxD \| RS232 Tx Line`
22			`watch IntTx \| Byte present in buffer`
23			`watch IntRx \| Emit Buffer is empty`
24			`watch BRClk`
25			`watch EnabTx EnabRx`
26
27			`\| Stimulators Assignment`
28			`\| 1/Write Byte`
29			`\| 2/Write another byte`
30			`\| 3/Read Byte`
31			`\| 4/Read Byte`
32			`clock WB_CLK_I 1 0`
33			`wfm WB_RST_I @1nS=L 100nS=H 100nS=L`
34			`wfm WB_STB_I @1nS=L +`
35			`@100.001uS=H 100nS=L +`
36			`@200.001uS=H 100nS=L +`
37			`@250.001uS=H 100nS=L +`
38			`@355.501uS=H 100nS=L`
39			`wfm WB_WE_I @1nS=L +`
40			`@100.001uS=H +`
41			`@200.001uS=L +`
42			`@250.001uS=H +`
43			`@355.501uS=L`
44			`wfm WB_ADR @1nS=L +`
45			`@100.001uS=0\H 100nS=Z +`
46			`@200.001uS=0\H 100nS=Z +`
47			`@250.001uS=0\H 100nS=Z +`
48			`@355.501uS=0\H 100nS=Z`
49			`wfm WB_DI @1nS=\0H +`
50			`@100.001uS=81\H 101nS=Z +`
51			`@250.001uS=55\H 101nS=Z`
52			`wfm BRClk @0nS=L (500nS=H 500nS=L)*500`
53
54			`\| Perform Simulation`
55			`sim 400uS`
56

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Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [sim/] [rtl_sim/] [bin/] [TESTUART.CMD] - Blame information for rev 26