OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] [orp.ld] - Blame information for rev 159

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 93 javieralso
MEMORY
2
        {
3
        reset   : ORIGIN = 0x00000000, LENGTH = 0x00000200
4
        vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
5
    ram     : ORIGIN = 0x00001200, LENGTH = 0x0001EE00  /*0x20000 total*/
6
        }
7
 
8
SECTIONS
9
{
10
        .reset :
11
        {
12
        *(.reset)
13
        } > reset
14
 
15
 
16
 
17
        .vectors :
18
        {
19
        _vec_start = .;
20
        *(.vectors)
21
        _vec_end = .;
22
        } > vectors
23
 
24
        .text :
25
        {
26
        *(.text)
27
        } > ram
28
 
29
      .rodata :
30
        {
31
        *(.rodata)
32
        *(.rodata.*)
33
        } > ram
34
 
35
     .icm :
36
        {
37
        _icm_start = .;
38
        *(.icm)
39
        _icm_end = .;
40
        } > ram
41
 
42
     .data :
43
        {
44
        _dst_beg = .;
45
        *(.data)
46
        _dst_end = .;
47
        } > ram
48
 
49
      .bss :
50
        {
51
        *(.bss)
52
        } > ram
53
 
54
      .stack (NOLOAD) :
55
        {
56
        *(.stack)
57
        _src_addr = .;
58
        } > ram
59
 
60
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.