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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's definitions ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Parameters of the OR1200 core ////
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//// ////
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//// To Do: ////
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//// - add parameters that are missing ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.44 2005/10/19 11:37:56 jcastillo
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// Added support for RAMB16 Xilinx4/Spartan3 primitives
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//
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// Revision 1.43 2005/01/07 09:23:39 andreje
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// l.ff1 and l.cmov instructions added
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//
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// Revision 1.42 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.41 2004/05/09 20:03:20 lampret
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// By default l.cust5 insns are disabled
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//
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// Revision 1.40 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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//
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// Revision 1.39 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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//
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// Revision 1.38 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.35.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
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// Static exception prefix.
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//
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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// Revision 1.34 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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//
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// Revision 1.33 2003/04/07 20:56:07 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
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//
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// Revision 1.32 2003/04/07 01:26:57 lampret
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// RFRAM defines comments updated. Altera LPM option added.
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//
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// Revision 1.31 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
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//
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Signal scanb_sen renamed to scanb_en.
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Removed obsolete comment.
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//
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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// Revision 1.25 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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// Revision 1.24 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.23 2002/09/04 00:50:34 lampret
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// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
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//
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// Revision 1.22 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.21 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.20 2002/08/18 21:59:45 lampret
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// Disable SB until it is tested
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//
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// Revision 1.19 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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//
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// Revision 1.17 2002/08/12 05:31:44 lampret
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// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
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//
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// Revision 1.16 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.15 2002/06/08 16:20:21 lampret
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// Added defines for enabling generic FF based memory macro for register file.
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//
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// Revision 1.14 2002/03/29 16:24:06 lampret
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// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
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//
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// Revision 1.13 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.12 2002/03/28 19:25:42 lampret
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// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
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//
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// Revision 1.11 2002/03/28 19:13:17 lampret
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// Updated defines.
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//
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// Revision 1.10 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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//
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// Revision 1.9 2002/03/11 01:26:26 lampret
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// Fixed async loop. Changed multiplier type for ASIC.
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//
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// Revision 1.8 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.7 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.6 2002/01/19 14:10:22 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.4 2002/01/14 09:44:12 lampret
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// Default ASIC configuration does not sample WB inputs.
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//
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// Revision 1.3 2002/01/08 00:51:08 lampret
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// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
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//
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// Revision 1.2 2002/01/03 21:23:03 lampret
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// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.20 2001/12/04 05:02:36 lampret
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// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
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//
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// Revision 1.19 2001/11/27 19:46:57 lampret
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// Now FPGA and ASIC target are separate.
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//
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.16 2001/11/20 21:30:38 lampret
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// Added OR1200_REGISTERED_INPUTS.
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//
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// Revision 1.15 2001/11/19 14:29:48 simons
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// Cashes disabled.
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//
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// Revision 1.14 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.13 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.12 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.11 2001/11/02 18:57:14 lampret
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// Modified virtual silicon instantiations.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.8 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.3 2001/08/17 08:01:19 lampret
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// IC enable/disable.
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//
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// Revision 1.2 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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rfajardo |
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//
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// Dump VCD
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//
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//`define OR1200_VCD_DUMP
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//
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// Generate debug messages during simulation
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//
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//`define OR1200_VERBOSE
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// `define OR1200_ASIC
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////////////////////////////////////////////////////////
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//
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// Typical configuration for an ASIC
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//
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`ifdef OR1200_ASIC
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//
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// Target ASIC memories
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//
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//`define OR1200_ARTISAN_SSP
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//`define OR1200_ARTISAN_SDP
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//`define OR1200_ARTISAN_STP
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`define OR1200_VIRTUALSILICON_SSP
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//`define OR1200_VIRTUALSILICON_STP_T1
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//`define OR1200_VIRTUALSILICON_STP_T2
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//
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// Do not implement Data cache
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//
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//`define OR1200_NO_DC
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//
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// Do not implement Insn cache
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//
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//`define OR1200_NO_IC
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//
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// Do not implement Data MMU
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//
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//`define OR1200_NO_DMMU
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//
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// Do not implement Insn MMU
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//
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//`define OR1200_NO_IMMU
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//
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// Select between ASIC optimized and generic multiplier
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//
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//`define OR1200_ASIC_MULTP2_32X32
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`define OR1200_GENERIC_MULTP2_32X32
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//
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// Size/type of insn/data cache if implemented
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//
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// `define OR1200_IC_1W_512B
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// `define OR1200_IC_1W_4KB
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`define OR1200_IC_1W_8KB
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// `define OR1200_DC_1W_4KB
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`define OR1200_DC_1W_8KB
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`else
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/////////////////////////////////////////////////////////
|
| 316 |
|
|
//
|
| 317 |
|
|
// Typical configuration for an FPGA
|
| 318 |
|
|
//
|
| 319 |
|
|
|
| 320 |
|
|
//
|
| 321 |
|
|
// Target FPGA memories
|
| 322 |
|
|
//
|
| 323 |
|
|
//`define OR1200_ALTERA_LPM
|
| 324 |
113 |
rfajardo |
`define OR1200_XILINX_RAMB16
|
| 325 |
66 |
rfajardo |
//`define OR1200_XILINX_RAMB4
|
| 326 |
|
|
//`define OR1200_XILINX_RAM32X1D
|
| 327 |
|
|
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
|
| 328 |
|
|
|
| 329 |
|
|
//
|
| 330 |
|
|
// Do not implement Data cache
|
| 331 |
|
|
//
|
| 332 |
|
|
`define OR1200_NO_DC
|
| 333 |
|
|
|
| 334 |
|
|
//
|
| 335 |
|
|
// Do not implement Insn cache
|
| 336 |
|
|
//
|
| 337 |
|
|
`define OR1200_NO_IC
|
| 338 |
|
|
|
| 339 |
|
|
//
|
| 340 |
|
|
// Do not implement Data MMU
|
| 341 |
|
|
//
|
| 342 |
|
|
`define OR1200_NO_DMMU
|
| 343 |
|
|
|
| 344 |
|
|
//
|
| 345 |
|
|
// Do not implement Insn MMU
|
| 346 |
|
|
//
|
| 347 |
|
|
`define OR1200_NO_IMMU
|
| 348 |
|
|
|
| 349 |
|
|
//
|
| 350 |
|
|
// Select between ASIC and generic multiplier
|
| 351 |
|
|
//
|
| 352 |
|
|
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
|
| 353 |
|
|
//
|
| 354 |
|
|
//`define OR1200_ASIC_MULTP2_32X32
|
| 355 |
|
|
`define OR1200_GENERIC_MULTP2_32X32
|
| 356 |
|
|
|
| 357 |
|
|
//
|
| 358 |
|
|
// Size/type of insn/data cache if implemented
|
| 359 |
|
|
// (consider available FPGA memory resources)
|
| 360 |
|
|
//
|
| 361 |
|
|
//`define OR1200_IC_1W_512B
|
| 362 |
113 |
rfajardo |
`define OR1200_IC_1W_4KB
|
| 363 |
|
|
//`define OR1200_IC_1W_8KB
|
| 364 |
|
|
`define OR1200_DC_1W_4KB
|
| 365 |
|
|
//`define OR1200_DC_1W_8KB
|
| 366 |
66 |
rfajardo |
|
| 367 |
|
|
`endif
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
//////////////////////////////////////////////////////////
|
| 371 |
|
|
//
|
| 372 |
|
|
// Do not change below unless you know what you are doing
|
| 373 |
|
|
//
|
| 374 |
|
|
|
| 375 |
|
|
//
|
| 376 |
|
|
// Enable RAM BIST
|
| 377 |
|
|
//
|
| 378 |
|
|
// At the moment this only works for Virtual Silicon
|
| 379 |
|
|
// single port RAMs. For other RAMs it has not effect.
|
| 380 |
|
|
// Special wrapper for VS RAMs needs to be provided
|
| 381 |
|
|
// with scan flops to facilitate bist scan.
|
| 382 |
|
|
//
|
| 383 |
|
|
//`define OR1200_BIST
|
| 384 |
|
|
|
| 385 |
|
|
//
|
| 386 |
|
|
// Register OR1200 WISHBONE outputs
|
| 387 |
|
|
// (must be defined/enabled)
|
| 388 |
|
|
//
|
| 389 |
|
|
`define OR1200_REGISTERED_OUTPUTS
|
| 390 |
|
|
|
| 391 |
|
|
//
|
| 392 |
|
|
// Register OR1200 WISHBONE inputs
|
| 393 |
|
|
//
|
| 394 |
|
|
// (must be undefined/disabled)
|
| 395 |
|
|
//
|
| 396 |
|
|
//`define OR1200_REGISTERED_INPUTS
|
| 397 |
|
|
|
| 398 |
|
|
//
|
| 399 |
|
|
// Disable bursts if they are not supported by the
|
| 400 |
|
|
// memory subsystem (only affect cache line fill)
|
| 401 |
|
|
//
|
| 402 |
|
|
//`define OR1200_NO_BURSTS
|
| 403 |
|
|
//
|
| 404 |
|
|
|
| 405 |
|
|
//
|
| 406 |
|
|
// WISHBONE retry counter range
|
| 407 |
|
|
//
|
| 408 |
|
|
// 2^value range for retry counter. Retry counter
|
| 409 |
|
|
// is activated whenever *wb_rty_i is asserted and
|
| 410 |
|
|
// until retry counter expires, corresponding
|
| 411 |
|
|
// WISHBONE interface is deactivated.
|
| 412 |
|
|
//
|
| 413 |
|
|
// To disable retry counters and *wb_rty_i all together,
|
| 414 |
|
|
// undefine this macro.
|
| 415 |
|
|
//
|
| 416 |
|
|
//`define OR1200_WB_RETRY 7
|
| 417 |
|
|
|
| 418 |
|
|
//
|
| 419 |
|
|
// WISHBONE Consecutive Address Burst
|
| 420 |
|
|
//
|
| 421 |
|
|
// This was used prior to WISHBONE B3 specification
|
| 422 |
|
|
// to identify bursts. It is no longer needed but
|
| 423 |
|
|
// remains enabled for compatibility with old designs.
|
| 424 |
|
|
//
|
| 425 |
|
|
// To remove *wb_cab_o ports undefine this macro.
|
| 426 |
|
|
//
|
| 427 |
113 |
rfajardo |
`define OR1200_WB_CAB
|
| 428 |
66 |
rfajardo |
|
| 429 |
|
|
//
|
| 430 |
|
|
// WISHBONE B3 compatible interface
|
| 431 |
|
|
//
|
| 432 |
|
|
// This follows the WISHBONE B3 specification.
|
| 433 |
|
|
// It is not enabled by default because most
|
| 434 |
|
|
// designs still don't use WB b3.
|
| 435 |
|
|
//
|
| 436 |
|
|
// To enable *wb_cti_o/*wb_bte_o ports,
|
| 437 |
|
|
// define this macro.
|
| 438 |
|
|
//
|
| 439 |
113 |
rfajardo |
//`define OR1200_WB_B3
|
| 440 |
66 |
rfajardo |
|
| 441 |
|
|
//
|
| 442 |
|
|
// Enable additional synthesis directives if using
|
| 443 |
|
|
// _Synopsys_ synthesis tool
|
| 444 |
|
|
//
|
| 445 |
|
|
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
| 446 |
|
|
|
| 447 |
|
|
//
|
| 448 |
|
|
// Enables default statement in some case blocks
|
| 449 |
|
|
// and disables Synopsys synthesis directive full_case
|
| 450 |
|
|
//
|
| 451 |
|
|
// By default it is enabled. When disabled it
|
| 452 |
|
|
// can increase clock frequency.
|
| 453 |
|
|
//
|
| 454 |
|
|
`define OR1200_CASE_DEFAULT
|
| 455 |
|
|
|
| 456 |
|
|
//
|
| 457 |
|
|
// Operand width / register file address width
|
| 458 |
|
|
//
|
| 459 |
|
|
// (DO NOT CHANGE)
|
| 460 |
|
|
//
|
| 461 |
|
|
`define OR1200_OPERAND_WIDTH 32
|
| 462 |
|
|
`define OR1200_REGFILE_ADDR_WIDTH 5
|
| 463 |
|
|
|
| 464 |
|
|
//
|
| 465 |
|
|
// l.add/l.addi/l.and and optional l.addc/l.addic
|
| 466 |
|
|
// also set (compare) flag when result of their
|
| 467 |
|
|
// operation equals zero
|
| 468 |
|
|
//
|
| 469 |
|
|
// At the time of writing this, default or32
|
| 470 |
|
|
// C/C++ compiler doesn't generate code that
|
| 471 |
|
|
// would benefit from this optimization.
|
| 472 |
|
|
//
|
| 473 |
|
|
// By default this optimization is disabled to
|
| 474 |
|
|
// save area.
|
| 475 |
|
|
//
|
| 476 |
|
|
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
|
| 477 |
|
|
|
| 478 |
|
|
//
|
| 479 |
|
|
// Implement l.addc/l.addic instructions
|
| 480 |
|
|
//
|
| 481 |
|
|
// By default implementation of l.addc/l.addic
|
| 482 |
|
|
// instructions is enabled in case you need them.
|
| 483 |
|
|
// If you don't use them, then disable implementation
|
| 484 |
|
|
// to save area.
|
| 485 |
|
|
//
|
| 486 |
92 |
rfajardo |
`define OR1200_IMPL_ADDC
|
| 487 |
66 |
rfajardo |
|
| 488 |
|
|
//
|
| 489 |
|
|
// Implement carry bit SR[CY]
|
| 490 |
|
|
//
|
| 491 |
|
|
// By default implementation of SR[CY] is enabled
|
| 492 |
113 |
rfajardo |
// to be compliant with the simulator. However
|
| 493 |
|
|
// SR[CY] is explicitly only used by l.addc/l.addic
|
| 494 |
|
|
// instructions and if these two insns are not
|
| 495 |
66 |
rfajardo |
// implemented there is not much point having SR[CY].
|
| 496 |
|
|
//
|
| 497 |
92 |
rfajardo |
`define OR1200_IMPL_CY
|
| 498 |
66 |
rfajardo |
|
| 499 |
|
|
//
|
| 500 |
113 |
rfajardo |
// Implement optional l.div/l.divu instructions
|
| 501 |
92 |
rfajardo |
//
|
| 502 |
113 |
rfajardo |
// By default divide instructions are not implemented
|
| 503 |
|
|
// to save area and increase clock frequency. or32 C/C++
|
| 504 |
|
|
// compiler can use soft library for division.
|
| 505 |
92 |
rfajardo |
//
|
| 506 |
113 |
rfajardo |
// To implement divide, multiplier needs to be implemented.
|
| 507 |
92 |
rfajardo |
//
|
| 508 |
113 |
rfajardo |
//`define OR1200_IMPL_DIV
|
| 509 |
92 |
rfajardo |
|
| 510 |
|
|
//
|
| 511 |
66 |
rfajardo |
// Implement rotate in the ALU
|
| 512 |
|
|
//
|
| 513 |
|
|
// At the time of writing this, or32
|
| 514 |
|
|
// C/C++ compiler doesn't generate rotate
|
| 515 |
|
|
// instructions. However or32 assembler
|
| 516 |
|
|
// can assemble code that uses rotate insn.
|
| 517 |
|
|
// This means that rotate instructions
|
| 518 |
|
|
// must be used manually inserted.
|
| 519 |
|
|
//
|
| 520 |
|
|
// By default implementation of rotate
|
| 521 |
|
|
// is disabled to save area and increase
|
| 522 |
|
|
// clock frequency.
|
| 523 |
|
|
//
|
| 524 |
|
|
//`define OR1200_IMPL_ALU_ROTATE
|
| 525 |
|
|
|
| 526 |
|
|
//
|
| 527 |
|
|
// Type of ALU compare to implement
|
| 528 |
|
|
//
|
| 529 |
113 |
rfajardo |
// Try either one to find what yields
|
| 530 |
|
|
// higher clock frequencyin your case.
|
| 531 |
66 |
rfajardo |
//
|
| 532 |
|
|
//`define OR1200_IMPL_ALU_COMP1
|
| 533 |
113 |
rfajardo |
`define OR1200_IMPL_ALU_COMP2
|
| 534 |
66 |
rfajardo |
|
| 535 |
|
|
//
|
| 536 |
|
|
// Implement multiplier
|
| 537 |
|
|
//
|
| 538 |
|
|
// By default multiplier is implemented
|
| 539 |
|
|
//
|
| 540 |
|
|
`define OR1200_MULT_IMPLEMENTED
|
| 541 |
|
|
|
| 542 |
|
|
//
|
| 543 |
|
|
// Implement multiply-and-accumulate
|
| 544 |
|
|
//
|
| 545 |
|
|
// By default MAC is implemented. To
|
| 546 |
113 |
rfajardo |
// implement MAC, multiplier needs to be
|
| 547 |
66 |
rfajardo |
// implemented.
|
| 548 |
|
|
//
|
| 549 |
113 |
rfajardo |
`define OR1200_MAC_IMPLEMENTED
|
| 550 |
66 |
rfajardo |
|
| 551 |
|
|
//
|
| 552 |
113 |
rfajardo |
// Low power, slower multiplier
|
| 553 |
66 |
rfajardo |
//
|
| 554 |
113 |
rfajardo |
// Select between low-power (larger) multiplier
|
| 555 |
|
|
// and faster multiplier. The actual difference
|
| 556 |
|
|
// is only AND logic that prevents distribution
|
| 557 |
|
|
// of operands into the multiplier when instruction
|
| 558 |
|
|
// in execution is not multiply instruction
|
| 559 |
66 |
rfajardo |
//
|
| 560 |
113 |
rfajardo |
//`define OR1200_LOWPWR_MULT
|
| 561 |
66 |
rfajardo |
|
| 562 |
|
|
//
|
| 563 |
|
|
// Clock ratio RISC clock versus WB clock
|
| 564 |
|
|
//
|
| 565 |
|
|
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
| 566 |
|
|
// both defines
|
| 567 |
|
|
//
|
| 568 |
|
|
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
|
| 569 |
|
|
// and use clmode to set ratio
|
| 570 |
|
|
//
|
| 571 |
|
|
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
|
| 572 |
|
|
// clmode to set ratio
|
| 573 |
|
|
//
|
| 574 |
113 |
rfajardo |
`define OR1200_CLKDIV_2_SUPPORTED
|
| 575 |
66 |
rfajardo |
//`define OR1200_CLKDIV_4_SUPPORTED
|
| 576 |
|
|
|
| 577 |
|
|
//
|
| 578 |
|
|
// Type of register file RAM
|
| 579 |
|
|
//
|
| 580 |
|
|
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
|
| 581 |
|
|
//`define OR1200_RFRAM_TWOPORT
|
| 582 |
|
|
//
|
| 583 |
113 |
rfajardo |
// Memory macro dual port (see or1200_dpram_32x32.v)
|
| 584 |
|
|
//`define OR1200_RFRAM_DUALPORT
|
| 585 |
66 |
rfajardo |
//
|
| 586 |
|
|
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
|
| 587 |
113 |
rfajardo |
`define OR1200_RFRAM_GENERIC
|
| 588 |
66 |
rfajardo |
|
| 589 |
|
|
//
|
| 590 |
|
|
// Type of mem2reg aligner to implement.
|
| 591 |
|
|
//
|
| 592 |
|
|
// Once OR1200_IMPL_MEM2REG2 yielded faster
|
| 593 |
|
|
// circuit, however with today tools it will
|
| 594 |
|
|
// most probably give you slower circuit.
|
| 595 |
|
|
//
|
| 596 |
|
|
`define OR1200_IMPL_MEM2REG1
|
| 597 |
|
|
//`define OR1200_IMPL_MEM2REG2
|
| 598 |
|
|
|
| 599 |
|
|
//
|
| 600 |
|
|
// ALUOPs
|
| 601 |
|
|
//
|
| 602 |
113 |
rfajardo |
`define OR1200_ALUOP_WIDTH 4
|
| 603 |
|
|
`define OR1200_ALUOP_NOP 4'd4
|
| 604 |
|
|
/* Order defined by arith insns that have two source operands both in regs
|
| 605 |
|
|
(see binutils/include/opcode/or32.h) */
|
| 606 |
|
|
`define OR1200_ALUOP_ADD 4'd0
|
| 607 |
|
|
`define OR1200_ALUOP_ADDC 4'd1
|
| 608 |
|
|
`define OR1200_ALUOP_SUB 4'd2
|
| 609 |
|
|
`define OR1200_ALUOP_AND 4'd3
|
| 610 |
|
|
`define OR1200_ALUOP_OR 4'd4
|
| 611 |
|
|
`define OR1200_ALUOP_XOR 4'd5
|
| 612 |
|
|
`define OR1200_ALUOP_MUL 4'd6
|
| 613 |
|
|
`define OR1200_ALUOP_CUST5 4'd7
|
| 614 |
|
|
`define OR1200_ALUOP_SHROT 4'd8
|
| 615 |
|
|
`define OR1200_ALUOP_DIV 4'd9
|
| 616 |
|
|
`define OR1200_ALUOP_DIVU 4'd10
|
| 617 |
|
|
/* Order not specifically defined. */
|
| 618 |
|
|
`define OR1200_ALUOP_IMM 4'd11
|
| 619 |
|
|
`define OR1200_ALUOP_MOVHI 4'd12
|
| 620 |
|
|
`define OR1200_ALUOP_COMP 4'd13
|
| 621 |
|
|
`define OR1200_ALUOP_MTSR 4'd14
|
| 622 |
|
|
`define OR1200_ALUOP_MFSR 4'd15
|
| 623 |
|
|
`define OR1200_ALUOP_CMOV 4'd14
|
| 624 |
|
|
`define OR1200_ALUOP_FF1 4'd15
|
| 625 |
66 |
rfajardo |
//
|
| 626 |
|
|
// MACOPs
|
| 627 |
|
|
//
|
| 628 |
113 |
rfajardo |
`define OR1200_MACOP_WIDTH 2
|
| 629 |
|
|
`define OR1200_MACOP_NOP 2'b00
|
| 630 |
|
|
`define OR1200_MACOP_MAC 2'b01
|
| 631 |
|
|
`define OR1200_MACOP_MSB 2'b10
|
| 632 |
66 |
rfajardo |
|
| 633 |
|
|
//
|
| 634 |
|
|
// Shift/rotate ops
|
| 635 |
|
|
//
|
| 636 |
113 |
rfajardo |
`define OR1200_SHROTOP_WIDTH 2
|
| 637 |
|
|
`define OR1200_SHROTOP_NOP 2'd0
|
| 638 |
|
|
`define OR1200_SHROTOP_SLL 2'd0
|
| 639 |
|
|
`define OR1200_SHROTOP_SRL 2'd1
|
| 640 |
|
|
`define OR1200_SHROTOP_SRA 2'd2
|
| 641 |
|
|
`define OR1200_SHROTOP_ROR 2'd3
|
| 642 |
66 |
rfajardo |
|
| 643 |
|
|
// Execution cycles per instruction
|
| 644 |
113 |
rfajardo |
`define OR1200_MULTICYCLE_WIDTH 2
|
| 645 |
|
|
`define OR1200_ONE_CYCLE 2'd0
|
| 646 |
|
|
`define OR1200_TWO_CYCLES 2'd1
|
| 647 |
66 |
rfajardo |
|
| 648 |
|
|
// Operand MUX selects
|
| 649 |
|
|
`define OR1200_SEL_WIDTH 2
|
| 650 |
|
|
`define OR1200_SEL_RF 2'd0
|
| 651 |
|
|
`define OR1200_SEL_IMM 2'd1
|
| 652 |
|
|
`define OR1200_SEL_EX_FORW 2'd2
|
| 653 |
|
|
`define OR1200_SEL_WB_FORW 2'd3
|
| 654 |
|
|
|
| 655 |
|
|
//
|
| 656 |
|
|
// BRANCHOPs
|
| 657 |
|
|
//
|
| 658 |
|
|
`define OR1200_BRANCHOP_WIDTH 3
|
| 659 |
|
|
`define OR1200_BRANCHOP_NOP 3'd0
|
| 660 |
|
|
`define OR1200_BRANCHOP_J 3'd1
|
| 661 |
|
|
`define OR1200_BRANCHOP_JR 3'd2
|
| 662 |
|
|
`define OR1200_BRANCHOP_BAL 3'd3
|
| 663 |
|
|
`define OR1200_BRANCHOP_BF 3'd4
|
| 664 |
|
|
`define OR1200_BRANCHOP_BNF 3'd5
|
| 665 |
|
|
`define OR1200_BRANCHOP_RFE 3'd6
|
| 666 |
|
|
|
| 667 |
|
|
//
|
| 668 |
|
|
// LSUOPs
|
| 669 |
|
|
//
|
| 670 |
|
|
// Bit 0: sign extend
|
| 671 |
|
|
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
|
| 672 |
|
|
// Bit 3: 0 load, 1 store
|
| 673 |
|
|
`define OR1200_LSUOP_WIDTH 4
|
| 674 |
|
|
`define OR1200_LSUOP_NOP 4'b0000
|
| 675 |
|
|
`define OR1200_LSUOP_LBZ 4'b0010
|
| 676 |
|
|
`define OR1200_LSUOP_LBS 4'b0011
|
| 677 |
|
|
`define OR1200_LSUOP_LHZ 4'b0100
|
| 678 |
|
|
`define OR1200_LSUOP_LHS 4'b0101
|
| 679 |
|
|
`define OR1200_LSUOP_LWZ 4'b0110
|
| 680 |
|
|
`define OR1200_LSUOP_LWS 4'b0111
|
| 681 |
113 |
rfajardo |
`define OR1200_LSUOP_LD 4'b0001
|
| 682 |
|
|
`define OR1200_LSUOP_SD 4'b1000
|
| 683 |
|
|
`define OR1200_LSUOP_SB 4'b1010
|
| 684 |
|
|
`define OR1200_LSUOP_SH 4'b1100
|
| 685 |
|
|
`define OR1200_LSUOP_SW 4'b1110
|
| 686 |
66 |
rfajardo |
|
| 687 |
|
|
// FETCHOPs
|
| 688 |
|
|
`define OR1200_FETCHOP_WIDTH 1
|
| 689 |
|
|
`define OR1200_FETCHOP_NOP 1'b0
|
| 690 |
|
|
`define OR1200_FETCHOP_LW 1'b1
|
| 691 |
|
|
|
| 692 |
|
|
//
|
| 693 |
|
|
// Register File Write-Back OPs
|
| 694 |
|
|
//
|
| 695 |
|
|
// Bit 0: register file write enable
|
| 696 |
113 |
rfajardo |
// Bits 2-1: write-back mux selects
|
| 697 |
|
|
`define OR1200_RFWBOP_WIDTH 3
|
| 698 |
|
|
`define OR1200_RFWBOP_NOP 3'b000
|
| 699 |
|
|
`define OR1200_RFWBOP_ALU 3'b001
|
| 700 |
|
|
`define OR1200_RFWBOP_LSU 3'b011
|
| 701 |
|
|
`define OR1200_RFWBOP_SPRS 3'b101
|
| 702 |
|
|
`define OR1200_RFWBOP_LR 3'b111
|
| 703 |
66 |
rfajardo |
|
| 704 |
|
|
// Compare instructions
|
| 705 |
|
|
`define OR1200_COP_SFEQ 3'b000
|
| 706 |
|
|
`define OR1200_COP_SFNE 3'b001
|
| 707 |
|
|
`define OR1200_COP_SFGT 3'b010
|
| 708 |
|
|
`define OR1200_COP_SFGE 3'b011
|
| 709 |
|
|
`define OR1200_COP_SFLT 3'b100
|
| 710 |
|
|
`define OR1200_COP_SFLE 3'b101
|
| 711 |
|
|
`define OR1200_COP_X 3'b111
|
| 712 |
|
|
`define OR1200_SIGNED_COMPARE 'd3
|
| 713 |
|
|
`define OR1200_COMPOP_WIDTH 4
|
| 714 |
|
|
|
| 715 |
|
|
//
|
| 716 |
|
|
// TAGs for instruction bus
|
| 717 |
|
|
//
|
| 718 |
|
|
`define OR1200_ITAG_IDLE 4'h0 // idle bus
|
| 719 |
|
|
`define OR1200_ITAG_NI 4'h1 // normal insn
|
| 720 |
|
|
`define OR1200_ITAG_BE 4'hb // Bus error exception
|
| 721 |
|
|
`define OR1200_ITAG_PE 4'hc // Page fault exception
|
| 722 |
|
|
`define OR1200_ITAG_TE 4'hd // TLB miss exception
|
| 723 |
|
|
|
| 724 |
|
|
//
|
| 725 |
|
|
// TAGs for data bus
|
| 726 |
|
|
//
|
| 727 |
|
|
`define OR1200_DTAG_IDLE 4'h0 // idle bus
|
| 728 |
|
|
`define OR1200_DTAG_ND 4'h1 // normal data
|
| 729 |
|
|
`define OR1200_DTAG_AE 4'ha // Alignment exception
|
| 730 |
|
|
`define OR1200_DTAG_BE 4'hb // Bus error exception
|
| 731 |
|
|
`define OR1200_DTAG_PE 4'hc // Page fault exception
|
| 732 |
|
|
`define OR1200_DTAG_TE 4'hd // TLB miss exception
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
//////////////////////////////////////////////
|
| 736 |
|
|
//
|
| 737 |
|
|
// ORBIS32 ISA specifics
|
| 738 |
|
|
//
|
| 739 |
|
|
|
| 740 |
|
|
// SHROT_OP position in machine word
|
| 741 |
|
|
`define OR1200_SHROTOP_POS 7:6
|
| 742 |
|
|
|
| 743 |
113 |
rfajardo |
// ALU instructions multicycle field in machine word
|
| 744 |
|
|
`define OR1200_ALUMCYC_POS 9:8
|
| 745 |
|
|
|
| 746 |
66 |
rfajardo |
//
|
| 747 |
|
|
// Instruction opcode groups (basic)
|
| 748 |
|
|
//
|
| 749 |
|
|
`define OR1200_OR32_J 6'b000000
|
| 750 |
|
|
`define OR1200_OR32_JAL 6'b000001
|
| 751 |
|
|
`define OR1200_OR32_BNF 6'b000011
|
| 752 |
|
|
`define OR1200_OR32_BF 6'b000100
|
| 753 |
|
|
`define OR1200_OR32_NOP 6'b000101
|
| 754 |
|
|
`define OR1200_OR32_MOVHI 6'b000110
|
| 755 |
|
|
`define OR1200_OR32_XSYNC 6'b001000
|
| 756 |
|
|
`define OR1200_OR32_RFE 6'b001001
|
| 757 |
|
|
/* */
|
| 758 |
|
|
`define OR1200_OR32_JR 6'b010001
|
| 759 |
|
|
`define OR1200_OR32_JALR 6'b010010
|
| 760 |
|
|
`define OR1200_OR32_MACI 6'b010011
|
| 761 |
|
|
/* */
|
| 762 |
|
|
`define OR1200_OR32_LWZ 6'b100001
|
| 763 |
|
|
`define OR1200_OR32_LBZ 6'b100011
|
| 764 |
|
|
`define OR1200_OR32_LBS 6'b100100
|
| 765 |
|
|
`define OR1200_OR32_LHZ 6'b100101
|
| 766 |
|
|
`define OR1200_OR32_LHS 6'b100110
|
| 767 |
|
|
`define OR1200_OR32_ADDI 6'b100111
|
| 768 |
|
|
`define OR1200_OR32_ADDIC 6'b101000
|
| 769 |
|
|
`define OR1200_OR32_ANDI 6'b101001
|
| 770 |
|
|
`define OR1200_OR32_ORI 6'b101010
|
| 771 |
|
|
`define OR1200_OR32_XORI 6'b101011
|
| 772 |
|
|
`define OR1200_OR32_MULI 6'b101100
|
| 773 |
|
|
`define OR1200_OR32_MFSPR 6'b101101
|
| 774 |
|
|
`define OR1200_OR32_SH_ROTI 6'b101110
|
| 775 |
|
|
`define OR1200_OR32_SFXXI 6'b101111
|
| 776 |
|
|
/* */
|
| 777 |
|
|
`define OR1200_OR32_MTSPR 6'b110000
|
| 778 |
|
|
`define OR1200_OR32_MACMSB 6'b110001
|
| 779 |
|
|
/* */
|
| 780 |
|
|
`define OR1200_OR32_SW 6'b110101
|
| 781 |
|
|
`define OR1200_OR32_SB 6'b110110
|
| 782 |
|
|
`define OR1200_OR32_SH 6'b110111
|
| 783 |
|
|
`define OR1200_OR32_ALU 6'b111000
|
| 784 |
|
|
`define OR1200_OR32_SFXX 6'b111001
|
| 785 |
113 |
rfajardo |
//`define OR1200_OR32_CUST5 6'b111100
|
| 786 |
66 |
rfajardo |
|
| 787 |
113 |
rfajardo |
|
| 788 |
66 |
rfajardo |
/////////////////////////////////////////////////////
|
| 789 |
|
|
//
|
| 790 |
|
|
// Exceptions
|
| 791 |
|
|
//
|
| 792 |
|
|
|
| 793 |
|
|
//
|
| 794 |
|
|
// Exception vectors per OR1K architecture:
|
| 795 |
|
|
// 0xPPPPP100 - reset
|
| 796 |
|
|
// 0xPPPPP200 - bus error
|
| 797 |
|
|
// ... etc
|
| 798 |
|
|
// where P represents exception prefix.
|
| 799 |
|
|
//
|
| 800 |
|
|
// Exception vectors can be customized as per
|
| 801 |
|
|
// the following formula:
|
| 802 |
|
|
// 0xPPPPPNVV - exception N
|
| 803 |
|
|
//
|
| 804 |
|
|
// P represents exception prefix
|
| 805 |
|
|
// N represents exception N
|
| 806 |
|
|
// VV represents length of the individual vector space,
|
| 807 |
|
|
// usually it is 8 bits wide and starts with all bits zero
|
| 808 |
|
|
//
|
| 809 |
|
|
|
| 810 |
|
|
//
|
| 811 |
|
|
// PPPPP and VV parts
|
| 812 |
|
|
//
|
| 813 |
|
|
// Sum of these two defines needs to be 28
|
| 814 |
|
|
//
|
| 815 |
113 |
rfajardo |
`define OR1200_EXCEPT_EPH0_P 20'h00000
|
| 816 |
|
|
`define OR1200_EXCEPT_EPH1_P 20'hF0000
|
| 817 |
|
|
`define OR1200_EXCEPT_V 8'h00
|
| 818 |
66 |
rfajardo |
|
| 819 |
|
|
//
|
| 820 |
|
|
// N part width
|
| 821 |
|
|
//
|
| 822 |
|
|
`define OR1200_EXCEPT_WIDTH 4
|
| 823 |
|
|
|
| 824 |
|
|
//
|
| 825 |
|
|
// Definition of exception vectors
|
| 826 |
|
|
//
|
| 827 |
|
|
// To avoid implementation of a certain exception,
|
| 828 |
|
|
// simply comment out corresponding line
|
| 829 |
|
|
//
|
| 830 |
|
|
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
|
| 831 |
|
|
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
|
| 832 |
113 |
rfajardo |
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
|
| 833 |
66 |
rfajardo |
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
|
| 834 |
|
|
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
|
| 835 |
|
|
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
|
| 836 |
|
|
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
|
| 837 |
|
|
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
|
| 838 |
|
|
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
|
| 839 |
|
|
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
|
| 840 |
|
|
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
|
| 841 |
|
|
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
|
| 842 |
|
|
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
|
| 843 |
|
|
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
|
| 844 |
|
|
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
|
| 845 |
|
|
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
|
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
/////////////////////////////////////////////////////
|
| 849 |
|
|
//
|
| 850 |
|
|
// SPR groups
|
| 851 |
|
|
//
|
| 852 |
|
|
|
| 853 |
|
|
// Bits that define the group
|
| 854 |
|
|
`define OR1200_SPR_GROUP_BITS 15:11
|
| 855 |
|
|
|
| 856 |
|
|
// Width of the group bits
|
| 857 |
|
|
`define OR1200_SPR_GROUP_WIDTH 5
|
| 858 |
|
|
|
| 859 |
|
|
// Bits that define offset inside the group
|
| 860 |
|
|
`define OR1200_SPR_OFS_BITS 10:0
|
| 861 |
|
|
|
| 862 |
|
|
// List of groups
|
| 863 |
|
|
`define OR1200_SPR_GROUP_SYS 5'd00
|
| 864 |
|
|
`define OR1200_SPR_GROUP_DMMU 5'd01
|
| 865 |
|
|
`define OR1200_SPR_GROUP_IMMU 5'd02
|
| 866 |
|
|
`define OR1200_SPR_GROUP_DC 5'd03
|
| 867 |
|
|
`define OR1200_SPR_GROUP_IC 5'd04
|
| 868 |
|
|
`define OR1200_SPR_GROUP_MAC 5'd05
|
| 869 |
|
|
`define OR1200_SPR_GROUP_DU 5'd06
|
| 870 |
|
|
`define OR1200_SPR_GROUP_PM 5'd08
|
| 871 |
|
|
`define OR1200_SPR_GROUP_PIC 5'd09
|
| 872 |
|
|
`define OR1200_SPR_GROUP_TT 5'd10
|
| 873 |
|
|
|
| 874 |
113 |
rfajardo |
|
| 875 |
66 |
rfajardo |
/////////////////////////////////////////////////////
|
| 876 |
|
|
//
|
| 877 |
|
|
// System group
|
| 878 |
|
|
//
|
| 879 |
|
|
|
| 880 |
|
|
//
|
| 881 |
|
|
// System registers
|
| 882 |
|
|
//
|
| 883 |
|
|
`define OR1200_SPR_CFGR 7'd0
|
| 884 |
|
|
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
|
| 885 |
|
|
`define OR1200_SPR_NPC 11'd16
|
| 886 |
|
|
`define OR1200_SPR_SR 11'd17
|
| 887 |
|
|
`define OR1200_SPR_PPC 11'd18
|
| 888 |
|
|
`define OR1200_SPR_EPCR 11'd32
|
| 889 |
|
|
`define OR1200_SPR_EEAR 11'd48
|
| 890 |
|
|
`define OR1200_SPR_ESR 11'd64
|
| 891 |
|
|
|
| 892 |
|
|
//
|
| 893 |
|
|
// SR bits
|
| 894 |
|
|
//
|
| 895 |
113 |
rfajardo |
`define OR1200_SR_WIDTH 16
|
| 896 |
66 |
rfajardo |
`define OR1200_SR_SM 0
|
| 897 |
|
|
`define OR1200_SR_TEE 1
|
| 898 |
|
|
`define OR1200_SR_IEE 2
|
| 899 |
|
|
`define OR1200_SR_DCE 3
|
| 900 |
|
|
`define OR1200_SR_ICE 4
|
| 901 |
|
|
`define OR1200_SR_DME 5
|
| 902 |
|
|
`define OR1200_SR_IME 6
|
| 903 |
|
|
`define OR1200_SR_LEE 7
|
| 904 |
|
|
`define OR1200_SR_CE 8
|
| 905 |
|
|
`define OR1200_SR_F 9
|
| 906 |
113 |
rfajardo |
`define OR1200_SR_CY 10 // Unused
|
| 907 |
|
|
`define OR1200_SR_OV 11 // Unused
|
| 908 |
|
|
`define OR1200_SR_OVE 12 // Unused
|
| 909 |
66 |
rfajardo |
`define OR1200_SR_DSX 13 // Unused
|
| 910 |
|
|
`define OR1200_SR_EPH 14
|
| 911 |
|
|
`define OR1200_SR_FO 15
|
| 912 |
|
|
`define OR1200_SR_CID 31:28 // Unimplemented
|
| 913 |
|
|
|
| 914 |
|
|
//
|
| 915 |
|
|
// Bits that define offset inside the group
|
| 916 |
|
|
//
|
| 917 |
|
|
`define OR1200_SPROFS_BITS 10:0
|
| 918 |
|
|
|
| 919 |
|
|
//
|
| 920 |
|
|
// Default Exception Prefix
|
| 921 |
|
|
//
|
| 922 |
|
|
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
|
| 923 |
|
|
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
|
| 924 |
|
|
//
|
| 925 |
|
|
`define OR1200_SR_EPH_DEF 1'b0
|
| 926 |
|
|
|
| 927 |
|
|
/////////////////////////////////////////////////////
|
| 928 |
|
|
//
|
| 929 |
|
|
// Power Management (PM)
|
| 930 |
|
|
//
|
| 931 |
|
|
|
| 932 |
|
|
// Define it if you want PM implemented
|
| 933 |
|
|
//`define OR1200_PM_IMPLEMENTED
|
| 934 |
|
|
|
| 935 |
|
|
// Bit positions inside PMR (don't change)
|
| 936 |
|
|
`define OR1200_PM_PMR_SDF 3:0
|
| 937 |
|
|
`define OR1200_PM_PMR_DME 4
|
| 938 |
|
|
`define OR1200_PM_PMR_SME 5
|
| 939 |
|
|
`define OR1200_PM_PMR_DCGE 6
|
| 940 |
|
|
`define OR1200_PM_PMR_UNUSED 31:7
|
| 941 |
|
|
|
| 942 |
|
|
// PMR offset inside PM group of registers
|
| 943 |
|
|
`define OR1200_PM_OFS_PMR 11'b0
|
| 944 |
|
|
|
| 945 |
|
|
// PM group
|
| 946 |
|
|
`define OR1200_SPRGRP_PM 5'd8
|
| 947 |
|
|
|
| 948 |
|
|
// Define if PMR can be read/written at any address inside PM group
|
| 949 |
|
|
`define OR1200_PM_PARTIAL_DECODING
|
| 950 |
|
|
|
| 951 |
|
|
// Define if reading PMR is allowed
|
| 952 |
|
|
`define OR1200_PM_READREGS
|
| 953 |
|
|
|
| 954 |
|
|
// Define if unused PMR bits should be zero
|
| 955 |
|
|
`define OR1200_PM_UNUSED_ZERO
|
| 956 |
|
|
|
| 957 |
|
|
|
| 958 |
|
|
/////////////////////////////////////////////////////
|
| 959 |
|
|
//
|
| 960 |
|
|
// Debug Unit (DU)
|
| 961 |
|
|
//
|
| 962 |
|
|
|
| 963 |
|
|
// Define it if you want DU implemented
|
| 964 |
|
|
`define OR1200_DU_IMPLEMENTED
|
| 965 |
|
|
|
| 966 |
|
|
//
|
| 967 |
|
|
// Define if you want HW Breakpoints
|
| 968 |
|
|
// (if HW breakpoints are not implemented
|
| 969 |
|
|
// only default software trapping is
|
| 970 |
|
|
// possible with l.trap insn - this is
|
| 971 |
|
|
// however already enough for use
|
| 972 |
|
|
// with or32 gdb)
|
| 973 |
|
|
//
|
| 974 |
113 |
rfajardo |
`define OR1200_DU_HWBKPTS
|
| 975 |
66 |
rfajardo |
|
| 976 |
|
|
// Number of DVR/DCR pairs if HW breakpoints enabled
|
| 977 |
|
|
`define OR1200_DU_DVRDCR_PAIRS 8
|
| 978 |
|
|
|
| 979 |
|
|
// Define if you want trace buffer
|
| 980 |
|
|
//`define OR1200_DU_TB_IMPLEMENTED
|
| 981 |
|
|
|
| 982 |
|
|
//
|
| 983 |
|
|
// Address offsets of DU registers inside DU group
|
| 984 |
|
|
//
|
| 985 |
|
|
// To not implement a register, doq not define its address
|
| 986 |
|
|
//
|
| 987 |
|
|
`ifdef OR1200_DU_HWBKPTS
|
| 988 |
|
|
`define OR1200_DU_DVR0 11'd0
|
| 989 |
|
|
`define OR1200_DU_DVR1 11'd1
|
| 990 |
|
|
`define OR1200_DU_DVR2 11'd2
|
| 991 |
|
|
`define OR1200_DU_DVR3 11'd3
|
| 992 |
|
|
`define OR1200_DU_DVR4 11'd4
|
| 993 |
|
|
`define OR1200_DU_DVR5 11'd5
|
| 994 |
|
|
`define OR1200_DU_DVR6 11'd6
|
| 995 |
|
|
`define OR1200_DU_DVR7 11'd7
|
| 996 |
|
|
`define OR1200_DU_DCR0 11'd8
|
| 997 |
|
|
`define OR1200_DU_DCR1 11'd9
|
| 998 |
|
|
`define OR1200_DU_DCR2 11'd10
|
| 999 |
|
|
`define OR1200_DU_DCR3 11'd11
|
| 1000 |
|
|
`define OR1200_DU_DCR4 11'd12
|
| 1001 |
|
|
`define OR1200_DU_DCR5 11'd13
|
| 1002 |
|
|
`define OR1200_DU_DCR6 11'd14
|
| 1003 |
|
|
`define OR1200_DU_DCR7 11'd15
|
| 1004 |
|
|
`endif
|
| 1005 |
|
|
`define OR1200_DU_DMR1 11'd16
|
| 1006 |
|
|
`ifdef OR1200_DU_HWBKPTS
|
| 1007 |
|
|
`define OR1200_DU_DMR2 11'd17
|
| 1008 |
|
|
`define OR1200_DU_DWCR0 11'd18
|
| 1009 |
|
|
`define OR1200_DU_DWCR1 11'd19
|
| 1010 |
|
|
`endif
|
| 1011 |
|
|
`define OR1200_DU_DSR 11'd20
|
| 1012 |
|
|
`define OR1200_DU_DRR 11'd21
|
| 1013 |
|
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
| 1014 |
|
|
`define OR1200_DU_TBADR 11'h0ff
|
| 1015 |
113 |
rfajardo |
`define OR1200_DU_TBIA 11'h1xx
|
| 1016 |
|
|
`define OR1200_DU_TBIM 11'h2xx
|
| 1017 |
|
|
`define OR1200_DU_TBAR 11'h3xx
|
| 1018 |
|
|
`define OR1200_DU_TBTS 11'h4xx
|
| 1019 |
66 |
rfajardo |
`endif
|
| 1020 |
|
|
|
| 1021 |
|
|
// Position of offset bits inside SPR address
|
| 1022 |
|
|
`define OR1200_DUOFS_BITS 10:0
|
| 1023 |
|
|
|
| 1024 |
|
|
// DCR bits
|
| 1025 |
|
|
`define OR1200_DU_DCR_DP 0
|
| 1026 |
|
|
`define OR1200_DU_DCR_CC 3:1
|
| 1027 |
|
|
`define OR1200_DU_DCR_SC 4
|
| 1028 |
|
|
`define OR1200_DU_DCR_CT 7:5
|
| 1029 |
|
|
|
| 1030 |
|
|
// DMR1 bits
|
| 1031 |
|
|
`define OR1200_DU_DMR1_CW0 1:0
|
| 1032 |
|
|
`define OR1200_DU_DMR1_CW1 3:2
|
| 1033 |
|
|
`define OR1200_DU_DMR1_CW2 5:4
|
| 1034 |
|
|
`define OR1200_DU_DMR1_CW3 7:6
|
| 1035 |
|
|
`define OR1200_DU_DMR1_CW4 9:8
|
| 1036 |
|
|
`define OR1200_DU_DMR1_CW5 11:10
|
| 1037 |
|
|
`define OR1200_DU_DMR1_CW6 13:12
|
| 1038 |
|
|
`define OR1200_DU_DMR1_CW7 15:14
|
| 1039 |
|
|
`define OR1200_DU_DMR1_CW8 17:16
|
| 1040 |
|
|
`define OR1200_DU_DMR1_CW9 19:18
|
| 1041 |
113 |
rfajardo |
`define OR1200_DU_DMR1_RES 21:20
|
| 1042 |
66 |
rfajardo |
`define OR1200_DU_DMR1_ST 22
|
| 1043 |
|
|
`define OR1200_DU_DMR1_BT 23
|
| 1044 |
|
|
|
| 1045 |
|
|
// DMR2 bits
|
| 1046 |
|
|
`define OR1200_DU_DMR2_WCE0 0
|
| 1047 |
|
|
`define OR1200_DU_DMR2_WCE1 1
|
| 1048 |
113 |
rfajardo |
`define OR1200_DU_DMR2_AWTC 11:2
|
| 1049 |
|
|
`define OR1200_DU_DMR2_WGB 21:12
|
| 1050 |
66 |
rfajardo |
|
| 1051 |
|
|
// DWCR bits
|
| 1052 |
|
|
`define OR1200_DU_DWCR_COUNT 15:0
|
| 1053 |
|
|
`define OR1200_DU_DWCR_MATCH 31:16
|
| 1054 |
|
|
|
| 1055 |
|
|
// DSR bits
|
| 1056 |
|
|
`define OR1200_DU_DSR_WIDTH 14
|
| 1057 |
|
|
`define OR1200_DU_DSR_RSTE 0
|
| 1058 |
|
|
`define OR1200_DU_DSR_BUSEE 1
|
| 1059 |
|
|
`define OR1200_DU_DSR_DPFE 2
|
| 1060 |
|
|
`define OR1200_DU_DSR_IPFE 3
|
| 1061 |
|
|
`define OR1200_DU_DSR_TTE 4
|
| 1062 |
|
|
`define OR1200_DU_DSR_AE 5
|
| 1063 |
|
|
`define OR1200_DU_DSR_IIE 6
|
| 1064 |
|
|
`define OR1200_DU_DSR_IE 7
|
| 1065 |
|
|
`define OR1200_DU_DSR_DME 8
|
| 1066 |
|
|
`define OR1200_DU_DSR_IME 9
|
| 1067 |
|
|
`define OR1200_DU_DSR_RE 10
|
| 1068 |
|
|
`define OR1200_DU_DSR_SCE 11
|
| 1069 |
113 |
rfajardo |
`define OR1200_DU_DSR_BE 12
|
| 1070 |
66 |
rfajardo |
`define OR1200_DU_DSR_TE 13
|
| 1071 |
|
|
|
| 1072 |
|
|
// DRR bits
|
| 1073 |
|
|
`define OR1200_DU_DRR_RSTE 0
|
| 1074 |
|
|
`define OR1200_DU_DRR_BUSEE 1
|
| 1075 |
|
|
`define OR1200_DU_DRR_DPFE 2
|
| 1076 |
|
|
`define OR1200_DU_DRR_IPFE 3
|
| 1077 |
|
|
`define OR1200_DU_DRR_TTE 4
|
| 1078 |
|
|
`define OR1200_DU_DRR_AE 5
|
| 1079 |
|
|
`define OR1200_DU_DRR_IIE 6
|
| 1080 |
|
|
`define OR1200_DU_DRR_IE 7
|
| 1081 |
|
|
`define OR1200_DU_DRR_DME 8
|
| 1082 |
|
|
`define OR1200_DU_DRR_IME 9
|
| 1083 |
|
|
`define OR1200_DU_DRR_RE 10
|
| 1084 |
|
|
`define OR1200_DU_DRR_SCE 11
|
| 1085 |
113 |
rfajardo |
`define OR1200_DU_DRR_BE 12
|
| 1086 |
66 |
rfajardo |
`define OR1200_DU_DRR_TE 13
|
| 1087 |
|
|
|
| 1088 |
|
|
// Define if reading DU regs is allowed
|
| 1089 |
|
|
`define OR1200_DU_READREGS
|
| 1090 |
|
|
|
| 1091 |
|
|
// Define if unused DU registers bits should be zero
|
| 1092 |
|
|
`define OR1200_DU_UNUSED_ZERO
|
| 1093 |
|
|
|
| 1094 |
|
|
// Define if IF/LSU status is not needed by devel i/f
|
| 1095 |
|
|
`define OR1200_DU_STATUS_UNIMPLEMENTED
|
| 1096 |
|
|
|
| 1097 |
|
|
/////////////////////////////////////////////////////
|
| 1098 |
|
|
//
|
| 1099 |
|
|
// Programmable Interrupt Controller (PIC)
|
| 1100 |
|
|
//
|
| 1101 |
|
|
|
| 1102 |
|
|
// Define it if you want PIC implemented
|
| 1103 |
|
|
`define OR1200_PIC_IMPLEMENTED
|
| 1104 |
|
|
|
| 1105 |
|
|
// Define number of interrupt inputs (2-31)
|
| 1106 |
|
|
`define OR1200_PIC_INTS 20
|
| 1107 |
|
|
|
| 1108 |
|
|
// Address offsets of PIC registers inside PIC group
|
| 1109 |
|
|
`define OR1200_PIC_OFS_PICMR 2'd0
|
| 1110 |
|
|
`define OR1200_PIC_OFS_PICSR 2'd2
|
| 1111 |
|
|
|
| 1112 |
|
|
// Position of offset bits inside SPR address
|
| 1113 |
|
|
`define OR1200_PICOFS_BITS 1:0
|
| 1114 |
|
|
|
| 1115 |
|
|
// Define if you want these PIC registers to be implemented
|
| 1116 |
|
|
`define OR1200_PIC_PICMR
|
| 1117 |
|
|
`define OR1200_PIC_PICSR
|
| 1118 |
|
|
|
| 1119 |
|
|
// Define if reading PIC registers is allowed
|
| 1120 |
|
|
`define OR1200_PIC_READREGS
|
| 1121 |
|
|
|
| 1122 |
|
|
// Define if unused PIC register bits should be zero
|
| 1123 |
|
|
`define OR1200_PIC_UNUSED_ZERO
|
| 1124 |
|
|
|
| 1125 |
|
|
|
| 1126 |
|
|
/////////////////////////////////////////////////////
|
| 1127 |
|
|
//
|
| 1128 |
|
|
// Tick Timer (TT)
|
| 1129 |
|
|
//
|
| 1130 |
|
|
|
| 1131 |
|
|
// Define it if you want TT implemented
|
| 1132 |
|
|
`define OR1200_TT_IMPLEMENTED
|
| 1133 |
|
|
|
| 1134 |
|
|
// Address offsets of TT registers inside TT group
|
| 1135 |
|
|
`define OR1200_TT_OFS_TTMR 1'd0
|
| 1136 |
|
|
`define OR1200_TT_OFS_TTCR 1'd1
|
| 1137 |
|
|
|
| 1138 |
|
|
// Position of offset bits inside SPR group
|
| 1139 |
|
|
`define OR1200_TTOFS_BITS 0
|
| 1140 |
|
|
|
| 1141 |
|
|
// Define if you want these TT registers to be implemented
|
| 1142 |
|
|
`define OR1200_TT_TTMR
|
| 1143 |
|
|
`define OR1200_TT_TTCR
|
| 1144 |
|
|
|
| 1145 |
|
|
// TTMR bits
|
| 1146 |
|
|
`define OR1200_TT_TTMR_TP 27:0
|
| 1147 |
|
|
`define OR1200_TT_TTMR_IP 28
|
| 1148 |
|
|
`define OR1200_TT_TTMR_IE 29
|
| 1149 |
|
|
`define OR1200_TT_TTMR_M 31:30
|
| 1150 |
|
|
|
| 1151 |
|
|
// Define if reading TT registers is allowed
|
| 1152 |
|
|
`define OR1200_TT_READREGS
|
| 1153 |
|
|
|
| 1154 |
|
|
|
| 1155 |
|
|
//////////////////////////////////////////////
|
| 1156 |
|
|
//
|
| 1157 |
|
|
// MAC
|
| 1158 |
|
|
//
|
| 1159 |
|
|
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
|
| 1160 |
|
|
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
|
| 1161 |
|
|
|
| 1162 |
|
|
//
|
| 1163 |
|
|
// Shift {MACHI,MACLO} into destination register when executing l.macrc
|
| 1164 |
|
|
//
|
| 1165 |
|
|
// According to architecture manual there is no shift, so default value is 0.
|
| 1166 |
113 |
rfajardo |
//
|
| 1167 |
|
|
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
|
| 1168 |
|
|
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
|
| 1169 |
|
|
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
|
| 1170 |
66 |
rfajardo |
// dest_GPR = {MACHI,MACLO}[59:28]
|
| 1171 |
|
|
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
|
| 1172 |
|
|
|
| 1173 |
|
|
|
| 1174 |
|
|
//////////////////////////////////////////////
|
| 1175 |
|
|
//
|
| 1176 |
|
|
// Data MMU (DMMU)
|
| 1177 |
|
|
//
|
| 1178 |
|
|
|
| 1179 |
|
|
//
|
| 1180 |
|
|
// Address that selects between TLB TR and MR
|
| 1181 |
|
|
//
|
| 1182 |
|
|
`define OR1200_DTLB_TM_ADDR 7
|
| 1183 |
|
|
|
| 1184 |
|
|
//
|
| 1185 |
|
|
// DTLBMR fields
|
| 1186 |
|
|
//
|
| 1187 |
|
|
`define OR1200_DTLBMR_V_BITS 0
|
| 1188 |
|
|
`define OR1200_DTLBMR_CID_BITS 4:1
|
| 1189 |
|
|
`define OR1200_DTLBMR_RES_BITS 11:5
|
| 1190 |
|
|
`define OR1200_DTLBMR_VPN_BITS 31:13
|
| 1191 |
|
|
|
| 1192 |
|
|
//
|
| 1193 |
|
|
// DTLBTR fields
|
| 1194 |
|
|
//
|
| 1195 |
|
|
`define OR1200_DTLBTR_CC_BITS 0
|
| 1196 |
|
|
`define OR1200_DTLBTR_CI_BITS 1
|
| 1197 |
|
|
`define OR1200_DTLBTR_WBC_BITS 2
|
| 1198 |
|
|
`define OR1200_DTLBTR_WOM_BITS 3
|
| 1199 |
|
|
`define OR1200_DTLBTR_A_BITS 4
|
| 1200 |
|
|
`define OR1200_DTLBTR_D_BITS 5
|
| 1201 |
|
|
`define OR1200_DTLBTR_URE_BITS 6
|
| 1202 |
|
|
`define OR1200_DTLBTR_UWE_BITS 7
|
| 1203 |
|
|
`define OR1200_DTLBTR_SRE_BITS 8
|
| 1204 |
|
|
`define OR1200_DTLBTR_SWE_BITS 9
|
| 1205 |
|
|
`define OR1200_DTLBTR_RES_BITS 11:10
|
| 1206 |
|
|
`define OR1200_DTLBTR_PPN_BITS 31:13
|
| 1207 |
|
|
|
| 1208 |
|
|
//
|
| 1209 |
|
|
// DTLB configuration
|
| 1210 |
|
|
//
|
| 1211 |
|
|
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
|
| 1212 |
|
|
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
|
| 1213 |
|
|
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
|
| 1214 |
|
|
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
|
| 1215 |
|
|
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
|
| 1216 |
|
|
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
|
| 1217 |
|
|
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
|
| 1218 |
|
|
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
|
| 1219 |
|
|
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
|
| 1220 |
|
|
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
|
| 1221 |
|
|
|
| 1222 |
|
|
//
|
| 1223 |
|
|
// Cache inhibit while DMMU is not enabled/implemented
|
| 1224 |
|
|
//
|
| 1225 |
|
|
// cache inhibited 0GB-4GB 1'b1
|
| 1226 |
|
|
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
|
| 1227 |
|
|
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
|
| 1228 |
|
|
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
|
| 1229 |
|
|
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
|
| 1230 |
|
|
// cached 0GB-4GB 1'b0
|
| 1231 |
|
|
//
|
| 1232 |
|
|
`define OR1200_DMMU_CI dcpu_adr_i[31]
|
| 1233 |
|
|
|
| 1234 |
|
|
|
| 1235 |
|
|
//////////////////////////////////////////////
|
| 1236 |
|
|
//
|
| 1237 |
|
|
// Insn MMU (IMMU)
|
| 1238 |
|
|
//
|
| 1239 |
|
|
|
| 1240 |
|
|
//
|
| 1241 |
|
|
// Address that selects between TLB TR and MR
|
| 1242 |
|
|
//
|
| 1243 |
|
|
`define OR1200_ITLB_TM_ADDR 7
|
| 1244 |
|
|
|
| 1245 |
|
|
//
|
| 1246 |
|
|
// ITLBMR fields
|
| 1247 |
|
|
//
|
| 1248 |
|
|
`define OR1200_ITLBMR_V_BITS 0
|
| 1249 |
|
|
`define OR1200_ITLBMR_CID_BITS 4:1
|
| 1250 |
|
|
`define OR1200_ITLBMR_RES_BITS 11:5
|
| 1251 |
|
|
`define OR1200_ITLBMR_VPN_BITS 31:13
|
| 1252 |
|
|
|
| 1253 |
|
|
//
|
| 1254 |
|
|
// ITLBTR fields
|
| 1255 |
|
|
//
|
| 1256 |
|
|
`define OR1200_ITLBTR_CC_BITS 0
|
| 1257 |
|
|
`define OR1200_ITLBTR_CI_BITS 1
|
| 1258 |
|
|
`define OR1200_ITLBTR_WBC_BITS 2
|
| 1259 |
|
|
`define OR1200_ITLBTR_WOM_BITS 3
|
| 1260 |
|
|
`define OR1200_ITLBTR_A_BITS 4
|
| 1261 |
|
|
`define OR1200_ITLBTR_D_BITS 5
|
| 1262 |
|
|
`define OR1200_ITLBTR_SXE_BITS 6
|
| 1263 |
|
|
`define OR1200_ITLBTR_UXE_BITS 7
|
| 1264 |
|
|
`define OR1200_ITLBTR_RES_BITS 11:8
|
| 1265 |
|
|
`define OR1200_ITLBTR_PPN_BITS 31:13
|
| 1266 |
|
|
|
| 1267 |
|
|
//
|
| 1268 |
|
|
// ITLB configuration
|
| 1269 |
|
|
//
|
| 1270 |
|
|
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
|
| 1271 |
|
|
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
|
| 1272 |
|
|
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
|
| 1273 |
|
|
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
|
| 1274 |
|
|
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
|
| 1275 |
|
|
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
|
| 1276 |
|
|
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
|
| 1277 |
|
|
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
|
| 1278 |
|
|
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
|
| 1279 |
|
|
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
|
| 1280 |
|
|
|
| 1281 |
|
|
//
|
| 1282 |
|
|
// Cache inhibit while IMMU is not enabled/implemented
|
| 1283 |
|
|
// Note: all combinations that use icpu_adr_i cause async loop
|
| 1284 |
|
|
//
|
| 1285 |
|
|
// cache inhibited 0GB-4GB 1'b1
|
| 1286 |
|
|
// cache inhibited 0GB-2GB !icpu_adr_i[31]
|
| 1287 |
|
|
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
|
| 1288 |
|
|
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
|
| 1289 |
|
|
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
|
| 1290 |
|
|
// cached 0GB-4GB 1'b0
|
| 1291 |
|
|
//
|
| 1292 |
|
|
`define OR1200_IMMU_CI 1'b0
|
| 1293 |
|
|
|
| 1294 |
|
|
|
| 1295 |
|
|
/////////////////////////////////////////////////
|
| 1296 |
|
|
//
|
| 1297 |
|
|
// Insn cache (IC)
|
| 1298 |
|
|
//
|
| 1299 |
|
|
|
| 1300 |
113 |
rfajardo |
// 3 for 8 bytes, 4 for 16 bytes etc
|
| 1301 |
|
|
`define OR1200_ICLS 4
|
| 1302 |
66 |
rfajardo |
|
| 1303 |
|
|
//
|
| 1304 |
|
|
// IC configurations
|
| 1305 |
|
|
//
|
| 1306 |
|
|
`ifdef OR1200_IC_1W_512B
|
| 1307 |
113 |
rfajardo |
`define OR1200_ICSIZE 9 // 512
|
| 1308 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
|
| 1309 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
|
| 1310 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
|
| 1311 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
|
| 1312 |
|
|
`define OR1200_ICTAG_W 24
|
| 1313 |
66 |
rfajardo |
`endif
|
| 1314 |
|
|
`ifdef OR1200_IC_1W_4KB
|
| 1315 |
|
|
`define OR1200_ICSIZE 12 // 4096
|
| 1316 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
|
| 1317 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
|
| 1318 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
|
| 1319 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
|
| 1320 |
|
|
`define OR1200_ICTAG_W 21
|
| 1321 |
|
|
`endif
|
| 1322 |
|
|
`ifdef OR1200_IC_1W_8KB
|
| 1323 |
|
|
`define OR1200_ICSIZE 13 // 8192
|
| 1324 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
|
| 1325 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
| 1326 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
| 1327 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
| 1328 |
|
|
`define OR1200_ICTAG_W 20
|
| 1329 |
|
|
`endif
|
| 1330 |
|
|
|
| 1331 |
|
|
|
| 1332 |
|
|
/////////////////////////////////////////////////
|
| 1333 |
|
|
//
|
| 1334 |
|
|
// Data cache (DC)
|
| 1335 |
|
|
//
|
| 1336 |
|
|
|
| 1337 |
113 |
rfajardo |
// 3 for 8 bytes, 4 for 16 bytes etc
|
| 1338 |
|
|
`define OR1200_DCLS 4
|
| 1339 |
66 |
rfajardo |
|
| 1340 |
113 |
rfajardo |
// Define to perform store refill (potential performance penalty)
|
| 1341 |
|
|
// `define OR1200_DC_STORE_REFILL
|
| 1342 |
66 |
rfajardo |
|
| 1343 |
|
|
//
|
| 1344 |
|
|
// DC configurations
|
| 1345 |
|
|
//
|
| 1346 |
|
|
`ifdef OR1200_DC_1W_4KB
|
| 1347 |
|
|
`define OR1200_DCSIZE 12 // 4096
|
| 1348 |
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
|
| 1349 |
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
|
| 1350 |
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
|
| 1351 |
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
|
| 1352 |
|
|
`define OR1200_DCTAG_W 21
|
| 1353 |
|
|
`endif
|
| 1354 |
|
|
`ifdef OR1200_DC_1W_8KB
|
| 1355 |
|
|
`define OR1200_DCSIZE 13 // 8192
|
| 1356 |
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
|
| 1357 |
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
| 1358 |
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
| 1359 |
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
| 1360 |
|
|
`define OR1200_DCTAG_W 20
|
| 1361 |
|
|
`endif
|
| 1362 |
|
|
|
| 1363 |
|
|
/////////////////////////////////////////////////
|
| 1364 |
|
|
//
|
| 1365 |
|
|
// Store buffer (SB)
|
| 1366 |
|
|
//
|
| 1367 |
|
|
|
| 1368 |
|
|
//
|
| 1369 |
|
|
// Store buffer
|
| 1370 |
|
|
//
|
| 1371 |
|
|
// It will improve performance by "caching" CPU stores
|
| 1372 |
|
|
// using store buffer. This is most important for function
|
| 1373 |
|
|
// prologues because DC can only work in write though mode
|
| 1374 |
|
|
// and all stores would have to complete external WB writes
|
| 1375 |
|
|
// to memory.
|
| 1376 |
|
|
// Store buffer is between DC and data BIU.
|
| 1377 |
|
|
// All stores will be stored into store buffer and immediately
|
| 1378 |
|
|
// completed by the CPU, even though actual external writes
|
| 1379 |
|
|
// will be performed later. As a consequence store buffer masks
|
| 1380 |
|
|
// all data bus errors related to stores (data bus errors
|
| 1381 |
|
|
// related to loads are delivered normally).
|
| 1382 |
|
|
// All pending CPU loads will wait until store buffer is empty to
|
| 1383 |
|
|
// ensure strict memory model. Right now this is necessary because
|
| 1384 |
|
|
// we don't make destinction between cached and cache inhibited
|
| 1385 |
|
|
// address space, so we simply empty store buffer until loads
|
| 1386 |
|
|
// can begin.
|
| 1387 |
|
|
//
|
| 1388 |
|
|
// It makes design a bit bigger, depending what is the number of
|
| 1389 |
|
|
// entries in SB FIFO. Number of entries can be changed further
|
| 1390 |
|
|
// down.
|
| 1391 |
|
|
//
|
| 1392 |
|
|
//`define OR1200_SB_IMPLEMENTED
|
| 1393 |
|
|
|
| 1394 |
|
|
//
|
| 1395 |
|
|
// Number of store buffer entries
|
| 1396 |
|
|
//
|
| 1397 |
|
|
// Verified number of entries are 4 and 8 entries
|
| 1398 |
|
|
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
|
| 1399 |
|
|
// always match 2**OR1200_SB_LOG.
|
| 1400 |
|
|
// To disable store buffer, undefine
|
| 1401 |
|
|
// OR1200_SB_IMPLEMENTED.
|
| 1402 |
|
|
//
|
| 1403 |
|
|
`define OR1200_SB_LOG 2 // 2 or 3
|
| 1404 |
|
|
`define OR1200_SB_ENTRIES 4 // 4 or 8
|
| 1405 |
|
|
|
| 1406 |
|
|
|
| 1407 |
|
|
/////////////////////////////////////////////////
|
| 1408 |
|
|
//
|
| 1409 |
|
|
// Quick Embedded Memory (QMEM)
|
| 1410 |
|
|
//
|
| 1411 |
|
|
|
| 1412 |
|
|
//
|
| 1413 |
|
|
// Quick Embedded Memory
|
| 1414 |
|
|
//
|
| 1415 |
|
|
// Instantiation of dedicated insn/data memory (RAM or ROM).
|
| 1416 |
|
|
// Insn fetch has effective throughput 1insn / clock cycle.
|
| 1417 |
|
|
// Data load takes two clock cycles / access, data store
|
| 1418 |
|
|
// takes 1 clock cycle / access (if there is no insn fetch)).
|
| 1419 |
|
|
// Memory instantiation is shared between insn and data,
|
| 1420 |
|
|
// meaning if insn fetch are performed, data load/store
|
| 1421 |
|
|
// performance will be lower.
|
| 1422 |
|
|
//
|
| 1423 |
|
|
// Main reason for QMEM is to put some time critical functions
|
| 1424 |
|
|
// into this memory and to have predictable and fast access
|
| 1425 |
|
|
// to these functions. (soft fpu, context switch, exception
|
| 1426 |
|
|
// handlers, stack, etc)
|
| 1427 |
|
|
//
|
| 1428 |
|
|
// It makes design a bit bigger and slower. QMEM sits behind
|
| 1429 |
|
|
// IMMU/DMMU so all addresses are physical (so the MMUs can be
|
| 1430 |
|
|
// used with QMEM and QMEM is seen by the CPU just like any other
|
| 1431 |
|
|
// memory in the system). IC/DC are sitting behind QMEM so the
|
| 1432 |
|
|
// whole design timing might be worse with QMEM implemented.
|
| 1433 |
|
|
//
|
| 1434 |
|
|
//`define OR1200_QMEM_IMPLEMENTED
|
| 1435 |
|
|
|
| 1436 |
|
|
//
|
| 1437 |
|
|
// Base address and mask of QMEM
|
| 1438 |
|
|
//
|
| 1439 |
|
|
// Base address defines first address of QMEM. Mask defines
|
| 1440 |
|
|
// QMEM range in address space. Actual size of QMEM is however
|
| 1441 |
|
|
// determined with instantiated RAM/ROM. However bigger
|
| 1442 |
|
|
// mask will reserve more address space for QMEM, but also
|
| 1443 |
|
|
// make design faster, while more tight mask will take
|
| 1444 |
|
|
// less address space but also make design slower. If
|
| 1445 |
|
|
// instantiated RAM/ROM is smaller than space reserved with
|
| 1446 |
|
|
// the mask, instatiated RAM/ROM will also be shadowed
|
| 1447 |
|
|
// at higher addresses in reserved space.
|
| 1448 |
|
|
//
|
| 1449 |
|
|
`define OR1200_QMEM_IADDR 32'h0080_0000
|
| 1450 |
113 |
rfajardo |
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
|
| 1451 |
|
|
`define OR1200_QMEM_DADDR 32'h0080_0000
|
| 1452 |
|
|
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
|
| 1453 |
66 |
rfajardo |
|
| 1454 |
|
|
//
|
| 1455 |
|
|
// QMEM interface byte-select capability
|
| 1456 |
|
|
//
|
| 1457 |
|
|
// To enable qmem_sel* ports, define this macro.
|
| 1458 |
|
|
//
|
| 1459 |
|
|
//`define OR1200_QMEM_BSEL
|
| 1460 |
|
|
|
| 1461 |
|
|
//
|
| 1462 |
|
|
// QMEM interface acknowledge
|
| 1463 |
|
|
//
|
| 1464 |
|
|
// To enable qmem_ack port, define this macro.
|
| 1465 |
|
|
//
|
| 1466 |
|
|
//`define OR1200_QMEM_ACK
|
| 1467 |
|
|
|
| 1468 |
|
|
/////////////////////////////////////////////////////
|
| 1469 |
|
|
//
|
| 1470 |
|
|
// VR, UPR and Configuration Registers
|
| 1471 |
|
|
//
|
| 1472 |
|
|
//
|
| 1473 |
|
|
// VR, UPR and configuration registers are optional. If
|
| 1474 |
|
|
// implemented, operating system can automatically figure
|
| 1475 |
|
|
// out how to use the processor because it knows
|
| 1476 |
|
|
// what units are available in the processor and how they
|
| 1477 |
|
|
// are configured.
|
| 1478 |
|
|
//
|
| 1479 |
|
|
// This section must be last in or1200_defines.v file so
|
| 1480 |
|
|
// that all units are already configured and thus
|
| 1481 |
|
|
// configuration registers are properly set.
|
| 1482 |
|
|
//
|
| 1483 |
|
|
|
| 1484 |
|
|
// Define if you want configuration registers implemented
|
| 1485 |
113 |
rfajardo |
//`define OR1200_CFGR_IMPLEMENTED
|
| 1486 |
66 |
rfajardo |
|
| 1487 |
|
|
// Define if you want full address decode inside SYS group
|
| 1488 |
|
|
`define OR1200_SYS_FULL_DECODE
|
| 1489 |
|
|
|
| 1490 |
|
|
// Offsets of VR, UPR and CFGR registers
|
| 1491 |
|
|
`define OR1200_SPRGRP_SYS_VR 4'h0
|
| 1492 |
|
|
`define OR1200_SPRGRP_SYS_UPR 4'h1
|
| 1493 |
|
|
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
|
| 1494 |
|
|
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
|
| 1495 |
|
|
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
|
| 1496 |
|
|
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
|
| 1497 |
|
|
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
|
| 1498 |
|
|
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
|
| 1499 |
|
|
|
| 1500 |
|
|
// VR fields
|
| 1501 |
|
|
`define OR1200_VR_REV_BITS 5:0
|
| 1502 |
|
|
`define OR1200_VR_RES1_BITS 15:6
|
| 1503 |
|
|
`define OR1200_VR_CFG_BITS 23:16
|
| 1504 |
|
|
`define OR1200_VR_VER_BITS 31:24
|
| 1505 |
|
|
|
| 1506 |
|
|
// VR values
|
| 1507 |
113 |
rfajardo |
`define OR1200_VR_REV 6'h01
|
| 1508 |
66 |
rfajardo |
`define OR1200_VR_RES1 10'h000
|
| 1509 |
|
|
`define OR1200_VR_CFG 8'h00
|
| 1510 |
|
|
`define OR1200_VR_VER 8'h12
|
| 1511 |
|
|
|
| 1512 |
|
|
// UPR fields
|
| 1513 |
|
|
`define OR1200_UPR_UP_BITS 0
|
| 1514 |
|
|
`define OR1200_UPR_DCP_BITS 1
|
| 1515 |
|
|
`define OR1200_UPR_ICP_BITS 2
|
| 1516 |
|
|
`define OR1200_UPR_DMP_BITS 3
|
| 1517 |
|
|
`define OR1200_UPR_IMP_BITS 4
|
| 1518 |
|
|
`define OR1200_UPR_MP_BITS 5
|
| 1519 |
|
|
`define OR1200_UPR_DUP_BITS 6
|
| 1520 |
|
|
`define OR1200_UPR_PCUP_BITS 7
|
| 1521 |
|
|
`define OR1200_UPR_PMP_BITS 8
|
| 1522 |
|
|
`define OR1200_UPR_PICP_BITS 9
|
| 1523 |
|
|
`define OR1200_UPR_TTP_BITS 10
|
| 1524 |
113 |
rfajardo |
`define OR1200_UPR_RES1_BITS 23:11
|
| 1525 |
66 |
rfajardo |
`define OR1200_UPR_CUP_BITS 31:24
|
| 1526 |
|
|
|
| 1527 |
|
|
// UPR values
|
| 1528 |
|
|
`define OR1200_UPR_UP 1'b1
|
| 1529 |
|
|
`ifdef OR1200_NO_DC
|
| 1530 |
|
|
`define OR1200_UPR_DCP 1'b0
|
| 1531 |
|
|
`else
|
| 1532 |
|
|
`define OR1200_UPR_DCP 1'b1
|
| 1533 |
|
|
`endif
|
| 1534 |
|
|
`ifdef OR1200_NO_IC
|
| 1535 |
|
|
`define OR1200_UPR_ICP 1'b0
|
| 1536 |
|
|
`else
|
| 1537 |
|
|
`define OR1200_UPR_ICP 1'b1
|
| 1538 |
|
|
`endif
|
| 1539 |
|
|
`ifdef OR1200_NO_DMMU
|
| 1540 |
|
|
`define OR1200_UPR_DMP 1'b0
|
| 1541 |
|
|
`else
|
| 1542 |
|
|
`define OR1200_UPR_DMP 1'b1
|
| 1543 |
|
|
`endif
|
| 1544 |
|
|
`ifdef OR1200_NO_IMMU
|
| 1545 |
|
|
`define OR1200_UPR_IMP 1'b0
|
| 1546 |
|
|
`else
|
| 1547 |
|
|
`define OR1200_UPR_IMP 1'b1
|
| 1548 |
|
|
`endif
|
| 1549 |
113 |
rfajardo |
`define OR1200_UPR_MP 1'b1 // MAC always present
|
| 1550 |
66 |
rfajardo |
`ifdef OR1200_DU_IMPLEMENTED
|
| 1551 |
|
|
`define OR1200_UPR_DUP 1'b1
|
| 1552 |
|
|
`else
|
| 1553 |
|
|
`define OR1200_UPR_DUP 1'b0
|
| 1554 |
|
|
`endif
|
| 1555 |
|
|
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
|
| 1556 |
113 |
rfajardo |
`ifdef OR1200_DU_IMPLEMENTED
|
| 1557 |
66 |
rfajardo |
`define OR1200_UPR_PMP 1'b1
|
| 1558 |
|
|
`else
|
| 1559 |
|
|
`define OR1200_UPR_PMP 1'b0
|
| 1560 |
|
|
`endif
|
| 1561 |
113 |
rfajardo |
`ifdef OR1200_DU_IMPLEMENTED
|
| 1562 |
66 |
rfajardo |
`define OR1200_UPR_PICP 1'b1
|
| 1563 |
|
|
`else
|
| 1564 |
|
|
`define OR1200_UPR_PICP 1'b0
|
| 1565 |
|
|
`endif
|
| 1566 |
113 |
rfajardo |
`ifdef OR1200_DU_IMPLEMENTED
|
| 1567 |
66 |
rfajardo |
`define OR1200_UPR_TTP 1'b1
|
| 1568 |
|
|
`else
|
| 1569 |
|
|
`define OR1200_UPR_TTP 1'b0
|
| 1570 |
|
|
`endif
|
| 1571 |
113 |
rfajardo |
`define OR1200_UPR_RES1 13'h0000
|
| 1572 |
66 |
rfajardo |
`define OR1200_UPR_CUP 8'h00
|
| 1573 |
|
|
|
| 1574 |
|
|
// CPUCFGR fields
|
| 1575 |
|
|
`define OR1200_CPUCFGR_NSGF_BITS 3:0
|
| 1576 |
113 |
rfajardo |
`define OR1200_CPUCFGR_HGF_BITS 4
|
| 1577 |
66 |
rfajardo |
`define OR1200_CPUCFGR_OB32S_BITS 5
|
| 1578 |
|
|
`define OR1200_CPUCFGR_OB64S_BITS 6
|
| 1579 |
|
|
`define OR1200_CPUCFGR_OF32S_BITS 7
|
| 1580 |
|
|
`define OR1200_CPUCFGR_OF64S_BITS 8
|
| 1581 |
|
|
`define OR1200_CPUCFGR_OV64S_BITS 9
|
| 1582 |
|
|
`define OR1200_CPUCFGR_RES1_BITS 31:10
|
| 1583 |
|
|
|
| 1584 |
|
|
// CPUCFGR values
|
| 1585 |
113 |
rfajardo |
`define OR1200_CPUCFGR_NSGF 4'h0
|
| 1586 |
|
|
`define OR1200_CPUCFGR_HGF 1'b0
|
| 1587 |
66 |
rfajardo |
`define OR1200_CPUCFGR_OB32S 1'b1
|
| 1588 |
|
|
`define OR1200_CPUCFGR_OB64S 1'b0
|
| 1589 |
113 |
rfajardo |
`define OR1200_CPUCFGR_OF32S 1'b0
|
| 1590 |
66 |
rfajardo |
`define OR1200_CPUCFGR_OF64S 1'b0
|
| 1591 |
|
|
`define OR1200_CPUCFGR_OV64S 1'b0
|
| 1592 |
|
|
`define OR1200_CPUCFGR_RES1 22'h000000
|
| 1593 |
|
|
|
| 1594 |
|
|
// DMMUCFGR fields
|
| 1595 |
|
|
`define OR1200_DMMUCFGR_NTW_BITS 1:0
|
| 1596 |
|
|
`define OR1200_DMMUCFGR_NTS_BITS 4:2
|
| 1597 |
|
|
`define OR1200_DMMUCFGR_NAE_BITS 7:5
|
| 1598 |
|
|
`define OR1200_DMMUCFGR_CRI_BITS 8
|
| 1599 |
|
|
`define OR1200_DMMUCFGR_PRI_BITS 9
|
| 1600 |
|
|
`define OR1200_DMMUCFGR_TEIRI_BITS 10
|
| 1601 |
|
|
`define OR1200_DMMUCFGR_HTR_BITS 11
|
| 1602 |
|
|
`define OR1200_DMMUCFGR_RES1_BITS 31:12
|
| 1603 |
|
|
|
| 1604 |
|
|
// DMMUCFGR values
|
| 1605 |
|
|
`ifdef OR1200_NO_DMMU
|
| 1606 |
|
|
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
|
| 1607 |
|
|
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
|
| 1608 |
|
|
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
|
| 1609 |
|
|
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
|
| 1610 |
|
|
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
|
| 1611 |
|
|
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
|
| 1612 |
|
|
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
|
| 1613 |
|
|
`define OR1200_DMMUCFGR_RES1 20'h00000
|
| 1614 |
|
|
`else
|
| 1615 |
|
|
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
|
| 1616 |
|
|
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
|
| 1617 |
|
|
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
|
| 1618 |
|
|
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
|
| 1619 |
|
|
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
|
| 1620 |
113 |
rfajardo |
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
|
| 1621 |
66 |
rfajardo |
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
|
| 1622 |
|
|
`define OR1200_DMMUCFGR_RES1 20'h00000
|
| 1623 |
|
|
`endif
|
| 1624 |
|
|
|
| 1625 |
|
|
// IMMUCFGR fields
|
| 1626 |
|
|
`define OR1200_IMMUCFGR_NTW_BITS 1:0
|
| 1627 |
|
|
`define OR1200_IMMUCFGR_NTS_BITS 4:2
|
| 1628 |
|
|
`define OR1200_IMMUCFGR_NAE_BITS 7:5
|
| 1629 |
|
|
`define OR1200_IMMUCFGR_CRI_BITS 8
|
| 1630 |
|
|
`define OR1200_IMMUCFGR_PRI_BITS 9
|
| 1631 |
|
|
`define OR1200_IMMUCFGR_TEIRI_BITS 10
|
| 1632 |
|
|
`define OR1200_IMMUCFGR_HTR_BITS 11
|
| 1633 |
|
|
`define OR1200_IMMUCFGR_RES1_BITS 31:12
|
| 1634 |
|
|
|
| 1635 |
|
|
// IMMUCFGR values
|
| 1636 |
|
|
`ifdef OR1200_NO_IMMU
|
| 1637 |
|
|
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
|
| 1638 |
|
|
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
|
| 1639 |
|
|
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
|
| 1640 |
|
|
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
|
| 1641 |
|
|
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
|
| 1642 |
|
|
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
|
| 1643 |
|
|
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
|
| 1644 |
|
|
`define OR1200_IMMUCFGR_RES1 20'h00000
|
| 1645 |
|
|
`else
|
| 1646 |
|
|
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
|
| 1647 |
|
|
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
|
| 1648 |
|
|
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
|
| 1649 |
|
|
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
|
| 1650 |
|
|
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
|
| 1651 |
113 |
rfajardo |
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
|
| 1652 |
66 |
rfajardo |
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
|
| 1653 |
|
|
`define OR1200_IMMUCFGR_RES1 20'h00000
|
| 1654 |
|
|
`endif
|
| 1655 |
|
|
|
| 1656 |
|
|
// DCCFGR fields
|
| 1657 |
|
|
`define OR1200_DCCFGR_NCW_BITS 2:0
|
| 1658 |
|
|
`define OR1200_DCCFGR_NCS_BITS 6:3
|
| 1659 |
|
|
`define OR1200_DCCFGR_CBS_BITS 7
|
| 1660 |
|
|
`define OR1200_DCCFGR_CWS_BITS 8
|
| 1661 |
|
|
`define OR1200_DCCFGR_CCRI_BITS 9
|
| 1662 |
|
|
`define OR1200_DCCFGR_CBIRI_BITS 10
|
| 1663 |
|
|
`define OR1200_DCCFGR_CBPRI_BITS 11
|
| 1664 |
|
|
`define OR1200_DCCFGR_CBLRI_BITS 12
|
| 1665 |
|
|
`define OR1200_DCCFGR_CBFRI_BITS 13
|
| 1666 |
|
|
`define OR1200_DCCFGR_CBWBRI_BITS 14
|
| 1667 |
|
|
`define OR1200_DCCFGR_RES1_BITS 31:15
|
| 1668 |
|
|
|
| 1669 |
|
|
// DCCFGR values
|
| 1670 |
|
|
`ifdef OR1200_NO_DC
|
| 1671 |
|
|
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
|
| 1672 |
|
|
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
|
| 1673 |
|
|
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
|
| 1674 |
|
|
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
|
| 1675 |
113 |
rfajardo |
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
|
| 1676 |
|
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
|
| 1677 |
66 |
rfajardo |
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
|
| 1678 |
|
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
|
| 1679 |
113 |
rfajardo |
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
|
| 1680 |
66 |
rfajardo |
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
|
| 1681 |
|
|
`define OR1200_DCCFGR_RES1 17'h00000
|
| 1682 |
|
|
`else
|
| 1683 |
|
|
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
|
| 1684 |
|
|
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
|
| 1685 |
113 |
rfajardo |
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
|
| 1686 |
|
|
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
|
| 1687 |
66 |
rfajardo |
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
|
| 1688 |
|
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
| 1689 |
|
|
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
| 1690 |
|
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
| 1691 |
|
|
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
| 1692 |
113 |
rfajardo |
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
|
| 1693 |
66 |
rfajardo |
`define OR1200_DCCFGR_RES1 17'h00000
|
| 1694 |
|
|
`endif
|
| 1695 |
|
|
|
| 1696 |
|
|
// ICCFGR fields
|
| 1697 |
|
|
`define OR1200_ICCFGR_NCW_BITS 2:0
|
| 1698 |
|
|
`define OR1200_ICCFGR_NCS_BITS 6:3
|
| 1699 |
|
|
`define OR1200_ICCFGR_CBS_BITS 7
|
| 1700 |
|
|
`define OR1200_ICCFGR_CWS_BITS 8
|
| 1701 |
|
|
`define OR1200_ICCFGR_CCRI_BITS 9
|
| 1702 |
|
|
`define OR1200_ICCFGR_CBIRI_BITS 10
|
| 1703 |
|
|
`define OR1200_ICCFGR_CBPRI_BITS 11
|
| 1704 |
|
|
`define OR1200_ICCFGR_CBLRI_BITS 12
|
| 1705 |
|
|
`define OR1200_ICCFGR_CBFRI_BITS 13
|
| 1706 |
|
|
`define OR1200_ICCFGR_CBWBRI_BITS 14
|
| 1707 |
|
|
`define OR1200_ICCFGR_RES1_BITS 31:15
|
| 1708 |
|
|
|
| 1709 |
|
|
// ICCFGR values
|
| 1710 |
|
|
`ifdef OR1200_NO_IC
|
| 1711 |
|
|
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
|
| 1712 |
|
|
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
|
| 1713 |
|
|
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
|
| 1714 |
|
|
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
|
| 1715 |
|
|
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
|
| 1716 |
|
|
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
|
| 1717 |
|
|
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
|
| 1718 |
|
|
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
|
| 1719 |
|
|
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
|
| 1720 |
|
|
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
|
| 1721 |
|
|
`define OR1200_ICCFGR_RES1 17'h00000
|
| 1722 |
|
|
`else
|
| 1723 |
|
|
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
|
| 1724 |
|
|
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
|
| 1725 |
113 |
rfajardo |
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
|
| 1726 |
66 |
rfajardo |
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
|
| 1727 |
|
|
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
|
| 1728 |
|
|
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
| 1729 |
|
|
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
| 1730 |
|
|
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
| 1731 |
|
|
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
| 1732 |
|
|
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
|
| 1733 |
|
|
`define OR1200_ICCFGR_RES1 17'h00000
|
| 1734 |
|
|
`endif
|
| 1735 |
|
|
|
| 1736 |
|
|
// DCFGR fields
|
| 1737 |
113 |
rfajardo |
`define OR1200_DCFGR_NDP_BITS 2:0
|
| 1738 |
|
|
`define OR1200_DCFGR_WPCI_BITS 3
|
| 1739 |
|
|
`define OR1200_DCFGR_RES1_BITS 31:4
|
| 1740 |
66 |
rfajardo |
|
| 1741 |
|
|
// DCFGR values
|
| 1742 |
|
|
`ifdef OR1200_DU_HWBKPTS
|
| 1743 |
113 |
rfajardo |
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
|
| 1744 |
66 |
rfajardo |
`ifdef OR1200_DU_DWCR0
|
| 1745 |
|
|
`define OR1200_DCFGR_WPCI 1'b1
|
| 1746 |
|
|
`else
|
| 1747 |
|
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
| 1748 |
|
|
`endif
|
| 1749 |
|
|
`else
|
| 1750 |
113 |
rfajardo |
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
|
| 1751 |
66 |
rfajardo |
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
| 1752 |
|
|
`endif
|
| 1753 |
113 |
rfajardo |
`define OR1200_DCFGR_RES1 28'h0000000
|
| 1754 |
|
|
|
