OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [board.h] - Blame information for rev 144

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
#ifndef _BOARD_H_
2
#define _BOARD_H_
3
 
4 53 ConX.
#define MC_ENABLED      0
5 2 rfajardo
 
6 53 ConX.
#define IC_ENABLE       0
7 2 rfajardo
#define IC_SIZE         8192
8 53 ConX.
#define DC_ENABLE       0
9 2 rfajardo
#define DC_SIZE         8192
10
 
11
 
12 53 ConX.
#define IN_CLK          25000000
13 2 rfajardo
 
14
 
15 53 ConX.
#define STACK_SIZE      0x01000
16 2 rfajardo
 
17
#define UART_BAUD_RATE  115200
18
 
19 53 ConX.
#define UART_BASE       0x90000000
20 2 rfajardo
#define UART_IRQ        2
21
#define ETH_BASE        0x92000000
22
#define ETH_IRQ         4
23 36 rfajardo
#define I2C_BASE        0x9D000000
24
#define I2C_IRQ         3
25
#define CAN_BASE        0x94000000
26
#define CAN_IRQ         5
27
 
28 2 rfajardo
#define MC_BASE_ADDR    0x60000000
29
#define SPI_BASE        0xa0000000
30
 
31 53 ConX.
#define ETH_DATA_BASE   0xa8000000 /*  Address for ETH_DATA */
32 2 rfajardo
 
33 53 ConX.
#define ETH_MACADDR0    0x00
34
#define ETH_MACADDR1    0x12
35 2 rfajardo
#define ETH_MACADDR2    0x34
36 53 ConX.
#define ETH_MACADDR3    0x56
37 2 rfajardo
#define ETH_MACADDR4    0x78
38 53 ConX.
#define ETH_MACADDR5    0x9a
39 2 rfajardo
 
40
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.