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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [blackboxes/] [adbg_top.v] - Blame information for rev 113

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1 63 rfajardo 
 
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`include "adbg_defines.v"
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module adbg_top(
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                // JTAG signals
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                tck_i,
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                tdi_i,
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                tdo_o,
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                rst_i,
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                // TAP states
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                shift_dr_i,
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                pause_dr_i,
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                update_dr_i,
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                capture_dr_i,
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                // Instructions
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                debug_select_i
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                `ifdef DBG_WISHBONE_SUPPORTED
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                // WISHBONE common signals
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                ,
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                wb_clk_i,
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                wb_rst_i,
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                // WISHBONE master interface
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                wb_adr_o,
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                wb_dat_o,
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                wb_dat_i,
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                wb_cyc_o,
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                wb_stb_o,
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                wb_sel_o,
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                wb_we_o,
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                wb_ack_i,
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                wb_cab_o,
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                wb_err_i,
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                wb_cti_o,
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                wb_bte_o
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                `endif
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                `ifdef DBG_CPU0_SUPPORTED
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                // CPU signals
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                ,
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                cpu0_clk_i,
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                cpu0_addr_o,
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                cpu0_data_i,
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                cpu0_data_o,
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                cpu0_bp_i,
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                cpu0_stall_o,
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                cpu0_stb_o,
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                cpu0_we_o,
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                cpu0_ack_i,
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                cpu0_rst_o
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                `endif
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                `ifdef DBG_CPU1_SUPPORTED
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                // CPU signals
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                ,
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                cpu1_clk_i,
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                cpu1_addr_o,
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                cpu1_data_i,
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                cpu1_data_o,
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                cpu1_bp_i,
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                cpu1_stall_o,
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                cpu1_stb_o,
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                cpu1_we_o,
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                cpu1_ack_i,
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                cpu1_rst_o
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                `endif
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                `ifdef DBG_JSP_SUPPORTED
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                ,
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                `ifndef DBG_WISHBONE_SUPPORTED
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                wb_clk_i,
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                wb_rst_i,
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                `endif
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                // WISHBONE target interface
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                wb_jsp_adr_i,
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                wb_jsp_dat_o,
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                wb_jsp_dat_i,
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                wb_jsp_cyc_i,
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                wb_jsp_stb_i,
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                wb_jsp_sel_i,
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                wb_jsp_we_i,
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                wb_jsp_ack_o,
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                wb_jsp_cab_i,
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                wb_jsp_err_o,
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                wb_jsp_cti_i,
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                wb_jsp_bte_i,
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                int_o
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                `endif
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                );
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   // JTAG signals
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   input   tck_i;
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   input   tdi_i;
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   output  tdo_o;
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   input   rst_i;
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   // TAP states
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   input   shift_dr_i;
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   input   pause_dr_i;
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   input   update_dr_i;
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   input   capture_dr_i;
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   // Module select from TAP
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   input   debug_select_i;
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`ifdef DBG_WISHBONE_SUPPORTED
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   input   wb_clk_i;
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   input   wb_rst_i;
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   output [31:0] wb_adr_o;
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   output [31:0] wb_dat_o;
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   input [31:0]  wb_dat_i;
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   output        wb_cyc_o;
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   output        wb_stb_o;
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   output [3:0]  wb_sel_o;
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   output        wb_we_o;
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   input         wb_ack_i;
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   output        wb_cab_o;
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   input         wb_err_i;
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   output [2:0]  wb_cti_o;
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   output [1:0]  wb_bte_o;
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`endif
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`ifdef DBG_CPU0_SUPPORTED
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   // CPU signals
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   input         cpu0_clk_i;
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   output [31:0] cpu0_addr_o;
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   input [31:0]  cpu0_data_i;
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   output [31:0] cpu0_data_o;
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   input         cpu0_bp_i;
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   output        cpu0_stall_o;
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   output        cpu0_stb_o;
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   output        cpu0_we_o;
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   input         cpu0_ack_i;
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   output        cpu0_rst_o;
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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   input         cpu1_clk_i;
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   output [31:0] cpu1_addr_o;
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   input [31:0]  cpu1_data_i;
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   output [31:0] cpu1_data_o;
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   input         cpu1_bp_i;
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   output        cpu1_stall_o;
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   output        cpu1_stb_o;
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   output        cpu1_we_o;
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   input         cpu1_ack_i;
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   output        cpu1_rst_o;
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`endif
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`ifdef DBG_JSP_SUPPORTED
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   `ifndef DBG_WISHBONE_SUPPORTED
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   input   wb_clk_i;
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   input   wb_rst_i;
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   `endif
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   input [31:0]  wb_jsp_adr_i;
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   output [31:0] wb_jsp_dat_o;
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   input [31:0]  wb_jsp_dat_i;
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   input         wb_jsp_cyc_i;
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   input         wb_jsp_stb_i;
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   input [3:0]   wb_jsp_sel_i;
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   input         wb_jsp_we_i;
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   output        wb_jsp_ack_o;
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   input         wb_jsp_cab_i;
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   output        wb_jsp_err_o;
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   input [2:0]   wb_jsp_cti_i;
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   input [1:0]   wb_jsp_bte_i;
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   output        int_o;
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`endif
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endmodule

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