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//////////////////////////////////////////////////////////////////////
////                                                              ////
////             Generic Wishbone controller for                  ////
////              Single-Port Synchronous RAM                     ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/minsoc/               ////
////                                                              ////
////  Description                                                 ////
////  This Wishbone controller connects to the wrapper of         ////
////  the single-port synchronous memory interface.               ////
////  Besides universal memory due to onchip_ram it provides a    ////
////  generic way to set the depth of the memory.                 ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Raul Fajardo, rfajardo@gmail.com                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.gnu.org/licenses/lgpl.html                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49      fajardo
// Not using the oe signal (output enable) from 
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Created interface and tested
//
 
 
module minsoc_onchip_ram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o
);
 
// 
// Parameters 
//
parameter    adr_width = 13;            //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam    aw_int = 11;              //11 = 2048
localparam    blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
 
// 
// I/O Ports 
// 
input      wb_clk_i;
input      wb_rst_i;
 
// 
// WB slave i/f 
// 
input  [31:0]   wb_dat_i;
output [31:0]   wb_dat_o;
input  [31:0]   wb_adr_i;
input  [3:0]    wb_sel_i;
input      wb_we_i;
input      wb_cyc_i;
input      wb_stb_i;
output     wb_ack_o;
output     wb_err_o;
 
// 
// Internal regs and wires 
// 
wire    we;
wire [3:0]  be_i;
wire [31:0]  wb_dat_o;
reg    ack_we;
reg    ack_re;
// 
// Aliases and simple assignments 
// 
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);  // If Access to > (8-bit leading prefix ignored) 
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
 
// 
// Write acknowledge 
// 
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
// 
// read acknowledge 
// 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_re <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
    ack_re <= #1 1'b1;
  else
    ack_re <= #1 1'b0;
end
 
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
 
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
 
generate
genvar j, k;
        for (j=0; j<slices; j=j+1) begin : SLICES
                for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
                        if (j==0) begin
                                mux2 #
                (
                    .dw(32)
                )
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ),
                    .in1( int_dat_o[k*2] ),
                                    .in2( int_dat_o[k*2+1] ),
                    .out( mux_out[k] )
                );
                        end
                        else begin
                                mux2 #
                (
                    .dw(32)
                )
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ),
                                    .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
                                    .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
                                    .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
                );
                        end
                end
        end
endgenerate
 
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
 
//(mux_in_nr-(mux_in_nr>>j)): 
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
 
wire [blocks-1:0] bank;
 
generate
genvar i;
    for (i=0; i < blocks; i=i+1) begin : MEM
 
        assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
 
        //BANK0
        minsoc_onchip_ram block_ram_0 (
            .clk(wb_clk_i),
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]),
            .di(wb_dat_i[7:0]),
            .doq(int_dat_o[i][7:0]),
            .we(we & bank[i]),
            .oe(1'b1),
            .ce(be_i[0])
        );
 
 
        minsoc_onchip_ram block_ram_1 (
            .clk(wb_clk_i),
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]),
            .di(wb_dat_i[15:8]),
            .doq(int_dat_o[i][15:8]),
            .we(we & bank[i]),
            .oe(1'b1),
            .ce(be_i[1])
        );
 
        minsoc_onchip_ram block_ram_2 (
            .clk(wb_clk_i),
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]),
            .di(wb_dat_i[23:16]),
            .doq(int_dat_o[i][23:16]),
            .we(we & bank[i]),
            .oe(1'b1),
            .ce(be_i[2])
        );
 
        minsoc_onchip_ram block_ram_3 (
            .clk(wb_clk_i),
            .rst(wb_rst_i),
            .addr(wb_adr_i[aw_int+1:2]),
            .di(wb_dat_i[31:24]),
            .doq(int_dat_o[i][31:24]),
            .we(we & bank[i]),
            .oe(1'b1),
            .ce(be_i[3])
        );
 
    end
endgenerate
 
endmodule
 
module mux2(sel,in1,in2,out);
 
parameter dw = 32;
 
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
 
always @ (sel or in1 or in2)
begin
        case (sel)
                1'b0: out = in1;
                1'b1: out = in2;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	2	rfajardo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Wishbone controller for ////`
4			`//// Single-Port Synchronous RAM ////`
5			`//// ////`
6			`//// This file is part of memory library available from ////`
7			`//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// This Wishbone controller connects to the wrapper of ////`
11			`//// the single-port synchronous memory interface. ////`
12			`//// Besides universal memory due to onchip_ram it provides a ////`
13			`//// generic way to set the depth of the memory. ////`
14			`//// ////`
15			`//// To Do: ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Raul Fajardo, rfajardo@gmail.com ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.gnu.org/licenses/lgpl.html ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// Revision History`
48			`//`
49	7	rfajardo	`// Revision 1.1 2009/10/02 16:49 fajardo`
50			`// Not using the oe signal (output enable) from`
51			`// memories, instead multiplexing the outputs`
52			`// between the different instantiated blocks`
53	2	rfajardo	`//`
54	7	rfajardo	`//`
55	2	rfajardo	`// Revision 1.0 2009/08/18 15:15:00 fajardo`
56			`// Created interface and tested`
57			`//`
58
59
60			`module minsoc_onchip_ram_top (`
61			`wb_clk_i, wb_rst_i,`
62
63			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
64			`wb_stb_i, wb_ack_o, wb_err_o`
65			`);`
66
67			`//`
68			`// Parameters`
69			`//`
70			`parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12`
71	7	rfajardo	`localparam aw_int = 11; //11 = 2048`
72			`localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data`
73	2	rfajardo
74			`//`
75			`// I/O Ports`
76			`//`
77			`input wb_clk_i;`
78			`input wb_rst_i;`
79
80			`//`
81			`// WB slave i/f`
82			`//`
83			`input [31:0] wb_dat_i;`
84			`output [31:0] wb_dat_o;`
85			`input [31:0] wb_adr_i;`
86			`input [3:0] wb_sel_i;`
87			`input wb_we_i;`
88			`input wb_cyc_i;`
89			`input wb_stb_i;`
90			`output wb_ack_o;`
91			`output wb_err_o;`
92
93			`//`
94			`// Internal regs and wires`
95			`//`
96			`wire we;`
97			`wire [3:0] be_i;`
98			`wire [31:0] wb_dat_o;`
99			`reg ack_we;`
100			`reg ack_re;`
101			`//`
102			`// Aliases and simple assignments`
103			`//`
104			`assign wb_ack_o = ack_re \| ack_we;`
105			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)`
106			`assign we = wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:0]);`
107			`assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;`
108
109			`//`
110			`// Write acknowledge`
111			`//`
112			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
113			`begin`
114			`if (wb_rst_i)`
115			`ack_we <= 1'b0;`
116			`else`
117			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
118			`ack_we <= #1 1'b1;`
119			`else`
120			`ack_we <= #1 1'b0;`
121			`end`
122
123			`//`
124			`// read acknowledge`
125			`//`
126			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
127			`begin`
128			`if (wb_rst_i)`
129			`ack_re <= 1'b0;`
130			`else`
131			`if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)`
132			`ack_re <= #1 1'b1;`
133			`else`
134			`ack_re <= #1 1'b0;`
135			`end`
136
137	7	rfajardo	`//Generic (multiple inputs x 1 output) MUX`
138			`localparam mux_in_nr = blocks;`
139			`localparam slices = adr_width-aw_int;`
140			`localparam mux_out_nr = blocks-1;`
141
142			`wire [31:0] int_dat_o[0:mux_in_nr-1];`
143			`wire [31:0] mux_out[0:mux_out_nr-1];`
144
145			`generate`
146			`genvar j, k;`
147			`for (j=0; j<slices; j=j+1) begin : SLICES`
148			`for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX`
149			`if (j==0) begin`
150			`mux2 #`
151			`(`
152			`.dw(32)`
153			`)`
154			`mux_int(`
155			`.sel( wb_adr_i[aw_int+2+j] ),`
156			`.in1( int_dat_o[k*2] ),`
157			`.in2( int_dat_o[k*2+1] ),`
158			`.out( mux_out[k] )`
159			`);`
160			`end`
161			`else begin`
162			`mux2 #`
163			`(`
164			`.dw(32)`
165			`)`
166			`mux_int(`
167			`.sel( wb_adr_i[aw_int+2+j] ),`
168			`.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),`
169			`.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),`
170			`.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )`
171			`);`
172			`end`
173			`end`
174			`end`
175			`endgenerate`
176
177			`//last output = total output`
178			`assign wb_dat_o = mux_out[mux_out_nr-1];`
179
180			`//(mux_in_nr-(mux_in_nr>>j)):`
181			`//-Given sum of 2^i \| i = x -> y series can be resumed to 2^(y+1)-2^x`
182			`//so, with this expression I'm evaluating how many times the internal loop has been run`
183
184	2	rfajardo	`wire [blocks-1:0] bank;`
185
186			`generate`
187			`genvar i;`
188			`for (i=0; i < blocks; i=i+1) begin : MEM`
189
190			`assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;`
191
192			`//BANK0`
193			`minsoc_onchip_ram block_ram_0 (`
194			`.clk(wb_clk_i),`
195			`.rst(wb_rst_i),`
196			`.addr(wb_adr_i[aw_int+1:2]),`
197			`.di(wb_dat_i[7:0]),`
198	7	rfajardo	`.doq(int_dat_o[i][7:0]),`
199	2	rfajardo	`.we(we & bank[i]),`
200	7	rfajardo	`.oe(1'b1),`
201			`.ce(be_i[0])`
202			`);`
203	2	rfajardo
204
205			`minsoc_onchip_ram block_ram_1 (`
206			`.clk(wb_clk_i),`
207			`.rst(wb_rst_i),`
208			`.addr(wb_adr_i[aw_int+1:2]),`
209			`.di(wb_dat_i[15:8]),`
210	7	rfajardo	`.doq(int_dat_o[i][15:8]),`
211	2	rfajardo	`.we(we & bank[i]),`
212	7	rfajardo	`.oe(1'b1),`
213			`.ce(be_i[1])`
214			`);`
215	2	rfajardo
216			`minsoc_onchip_ram block_ram_2 (`
217			`.clk(wb_clk_i),`
218			`.rst(wb_rst_i),`
219			`.addr(wb_adr_i[aw_int+1:2]),`
220			`.di(wb_dat_i[23:16]),`
221	7	rfajardo	`.doq(int_dat_o[i][23:16]),`
222	2	rfajardo	`.we(we & bank[i]),`
223	7	rfajardo	`.oe(1'b1),`
224			`.ce(be_i[2])`
225			`);`
226	2	rfajardo
227			`minsoc_onchip_ram block_ram_3 (`
228			`.clk(wb_clk_i),`
229			`.rst(wb_rst_i),`
230			`.addr(wb_adr_i[aw_int+1:2]),`
231			`.di(wb_dat_i[31:24]),`
232	7	rfajardo	`.doq(int_dat_o[i][31:24]),`
233	2	rfajardo	`.we(we & bank[i]),`
234	7	rfajardo	`.oe(1'b1),`
235			`.ce(be_i[3])`
236			`);`
237	2	rfajardo
238			`end`
239			`endgenerate`
240
241			`endmodule`
242
243	7	rfajardo	`module mux2(sel,in1,in2,out);`
244
245			`parameter dw = 32;`
246
247			`input sel;`
248			`input [dw-1:0] in1, in2;`
249			`output reg [dw-1:0] out;`
250
251			`always @ (sel or in1 or in2)`
252			`begin`
253			`case (sel)`
254			`1'b0: out = in1;`
255			`1'b1: out = in2;`
256			`endcase`
257			`end`
258
259			`endmodule`

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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [minsoc_onchip_ram_top.v] - Blame information for rev 167