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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [xilinx_dcm.v] - Blame information for rev 167

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`include "minsoc_defines.v"
 
module xilinx_dcm(
        clk_i,
        clk_o
);
 
// 
// Parameters 
// 
   parameter    divisor = 2;
 
input clk_i;
output clk_o;
 
 
`ifdef SPARTAN2
        `define XILINX_DLL
`elsif VIRTEX
        `define XILINX_DLL
`endif  // !SPARTAN2/VIRTEX
 
`ifdef SPARTAN3
        `define XILINX_DCM
`elsif VIRTEX2
        `define XILINX_DCM
`endif  // !SPARTAN3/VIRTEX2
 
`ifdef SPARTAN3E
        `define XILINX_DCM_SP
`elsif SPARTAN3A
        `define XILINX_DCM_SP
`endif  // !SPARTAN3E/SPARTAN3A
 
`ifdef VIRTEX4
        `define XILINX_DCM_ADV
        `define XILINX_DCM_COMPONENT "VIRTEX4"
`elsif VIRTEX5
        `define XILINX_DCM_ADV
        `define XILINX_DCM_COMPONENT "VIRTEX5"
`endif  // !VIRTEX4/VIRTEX5
 
 
wire CLKIN_IN;
wire CLKDV_OUT;
 
assign CLKIN_IN = clk_i;
assign clk_o = CLKDV_OUT;
 
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKDV_BUF;
 
`ifdef XILINX_FPGA
 
IBUFG CLKIN_IBUFG_INST (
        .I(CLKIN_IN),
        .O(CLKIN_IBUFG)
);
 
BUFG CLK0_BUFG_INST (
        .I(CLK0_BUF),
        .O(CLKFB_IN)
);
 
BUFG CLKDV_BUFG_INST (
        .I(CLKDV_BUF),
        .O(CLKDV_OUT)
);
 
`ifdef XILINX_DLL
 
CLKDLL #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .FACTORY_JF(16'hC080),                  // FACTORY JF Values
        .STARTUP_WAIT("FALSE")                  // Delay config DONE until DLL LOCK, TRUE/FALSE
) CLKDLL_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DLL CLK output
        .CLK180(),                              // 180 degree DLL CLK output
        .CLK270(),                              // 270 degree DLL CLK output
        .CLK2X(),                               // 2X DLL CLK output
        .CLK90(),                               // 90 degree DLL CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DLL CLK out (CLKDV_DIVIDE)
        .LOCKED(),                              // DLL LOCK status output
        .CLKFB(CLKFB_IN),                       // DLL clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DLL)
        .RST(1'b0)                              // DLL asynchronous reset input
);
 
`elsif XILINX_DCM
 
DCM #(
        .SIM_MODE("SAFE"),                      // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .FACTORY_JF(16'hC080),                  // FACTORY JF values
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .STATUS(),                              // 8-bit DCM status bits output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`elsif XILINX_DCM_SP
 
DCM_SP #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .STATUS(),                              // 8-bit DCM status bits output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`elsif XILINX_DCM_ADV
 
DCM_ADV #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(10.0),                    // Specify period of input clock in ns from 1.25 to 1000.00
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift mode of NONE, FIXED,
                                                // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DCM_AUTOCALIBRATION("TRUE"),           // DCM calibration circuitry "TRUE"/"FALSE"
        .DCM_PERFORMANCE_MODE("MAX_SPEED"),     // Can be MAX_SPEED or MAX_RANGE
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
        .DLL_FREQUENCY_MODE("LOW"),             // LOW, HIGH, or HIGH_SER frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, "TRUE"/"FALSE"
        .FACTORY_JF(16'hf0f0),                  // FACTORY JF value suggested to be set to 16’hf0f0
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 1023
        .SIM_DEVICE(`XILINX_DCM_COMPONENT),     // Set target device, "VIRTEX4" or "VIRTEX5"
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .DO(),                                  // 16-bit data output for Dynamic Reconfiguration Port (DRP)
        .DRDY(),                                // Ready output signal from the DRP
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .DADDR(7'h00),                          // 7-bit address for the DRP
        .DCLK(1'b0),                            // Clock for the DRP
        .DEN(1'b0),                             // Enable input for the DRP
        .DI(16'h0000),                          // 16-bit data input for the DRP
        .DWE(1'b0),                             // Active high allows for writing configuration memory
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`endif  // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
`endif  // !XILINX_FPGA
 
 
endmodule

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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [xilinx_dcm.v] - Blame information for rev 167

Line No.	Rev	Author	Line
1	62	rfajardo
2			`include "minsoc_defines.v"
3
4			`module xilinx_dcm(`
5			`clk_i,`
6			`clk_o`
7			`);`
8
9			`//`
10			`// Parameters`
11			`//`
12			`parameter divisor = 2;`
13
14			`input clk_i;`
15			`output clk_o;`
16
17
18			`ifdef SPARTAN2
19			`define XILINX_DLL
20			`elsif VIRTEX
21			`define XILINX_DLL
22			`endif // !SPARTAN2/VIRTEX
23
24			`ifdef SPARTAN3
25			`define XILINX_DCM
26			`elsif VIRTEX2
27			`define XILINX_DCM
28			`endif // !SPARTAN3/VIRTEX2
29
30			`ifdef SPARTAN3E
31			`define XILINX_DCM_SP
32			`elsif SPARTAN3A
33			`define XILINX_DCM_SP
34			`endif // !SPARTAN3E/SPARTAN3A
35
36			`ifdef VIRTEX4
37			`define XILINX_DCM_ADV
38			`define XILINX_DCM_COMPONENT "VIRTEX4"
39			`elsif VIRTEX5
40			`define XILINX_DCM_ADV
41			`define XILINX_DCM_COMPONENT "VIRTEX5"
42			`endif // !VIRTEX4/VIRTEX5
43
44
45			`wire CLKIN_IN;`
46			`wire CLKDV_OUT;`
47
48			`assign CLKIN_IN = clk_i;`
49			`assign clk_o = CLKDV_OUT;`
50
51			`wire CLKIN_IBUFG;`
52			`wire CLK0_BUF;`
53			`wire CLKFB_IN;`
54			`wire CLKDV_BUF;`
55
56	88	rfajardo	`ifdef XILINX_FPGA
57
58	62	rfajardo	`IBUFG CLKIN_IBUFG_INST (`
59			`.I(CLKIN_IN),`
60			`.O(CLKIN_IBUFG)`
61			`);`
62
63			`BUFG CLK0_BUFG_INST (`
64			`.I(CLK0_BUF),`
65			`.O(CLKFB_IN)`
66			`);`
67
68			`BUFG CLKDV_BUFG_INST (`
69			`.I(CLKDV_BUF),`
70			`.O(CLKDV_OUT)`
71			`);`
72
73			`ifdef XILINX_DLL
74
75			`CLKDLL #(`
76			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0`
77			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
78			`.FACTORY_JF(16'hC080), // FACTORY JF Values`
79			`.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE`
80			`) CLKDLL_inst (`
81			`.CLK0(CLK0_BUF), // 0 degree DLL CLK output`
82			`.CLK180(), // 180 degree DLL CLK output`
83			`.CLK270(), // 270 degree DLL CLK output`
84			`.CLK2X(), // 2X DLL CLK output`
85			`.CLK90(), // 90 degree DLL CLK output`
86			`.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)`
87			`.LOCKED(), // DLL LOCK status output`
88			`.CLKFB(CLKFB_IN), // DLL clock feedback`
89			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)`
90			`.RST(1'b0) // DLL asynchronous reset input`
91			`);`
92
93			`elsif XILINX_DCM
94
95			`DCM #(`
96			`.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details`
97			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
98			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
99			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
100			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
101			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
102			`.CLKIN_PERIOD(0.0), // Specify period of input clock`
103			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE`
104			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
105			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
106			`// an integer from 0 to 15`
107			`.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis`
108			`.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL`
109			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
110			`.FACTORY_JF(16'hC080), // FACTORY JF values`
111			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255`
112			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE`
113			`) DCM_inst (`
114			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
115			`.CLK180(), // 180 degree DCM CLK output`
116			`.CLK270(), // 270 degree DCM CLK output`
117			`.CLK2X(), // 2X DCM CLK output`
118			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
119			`.CLK90(), // 90 degree DCM CLK output`
120			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
121			`.CLKFX(), // DCM CLK synthesis out (M/D)`
122			`.CLKFX180(), // 180 degree CLK synthesis out`
123			`.LOCKED(), // DCM LOCK status output`
124			`.PSDONE(), // Dynamic phase adjust done output`
125			`.STATUS(), // 8-bit DCM status bits output`
126			`.CLKFB(CLKFB_IN), // DCM clock feedback`
127			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
128			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
129			`.PSEN(1'b0), // Dynamic phase adjust enable input`
130			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
131			`.RST(1'b0) // DCM asynchronous reset input`
132			`);`
133
134			`elsif XILINX_DCM_SP
135
136			`DCM_SP #(`
137			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
138			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
139			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
140			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
141			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
142			`.CLKIN_PERIOD(0.0), // Specify period of input clock`
143			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE`
144			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
145			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
146			`// an integer from 0 to 15`
147			`.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL`
148			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
149			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255`
150			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE`
151			`) DCM_SP_inst (`
152			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
153			`.CLK180(), // 180 degree DCM CLK output`
154			`.CLK270(), // 270 degree DCM CLK output`
155			`.CLK2X(), // 2X DCM CLK output`
156			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
157			`.CLK90(), // 90 degree DCM CLK output`
158			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
159			`.CLKFX(), // DCM CLK synthesis out (M/D)`
160			`.CLKFX180(), // 180 degree CLK synthesis out`
161			`.LOCKED(), // DCM LOCK status output`
162			`.PSDONE(), // Dynamic phase adjust done output`
163			`.STATUS(), // 8-bit DCM status bits output`
164			`.CLKFB(CLKFB_IN), // DCM clock feedback`
165			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
166			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
167			`.PSEN(1'b0), // Dynamic phase adjust enable input`
168			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
169			`.RST(1'b0) // DCM asynchronous reset input`
170			`);`
171
172			`elsif XILINX_DCM_ADV
173
174			`DCM_ADV #(`
175			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
176			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
177			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
178			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
179			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
180			`.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00`
181			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,`
182			`// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT`
183			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
184			`.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"`
185			`.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE`
186			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
187			`// an integer from 0 to 15`
188			`.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis`
189			`.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL`
190			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"`
191			`.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0`
192			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023`
193			.SIM_DEVICE(`XILINX_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
194			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"`
195			`) DCM_ADV_inst (`
196			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
197			`.CLK180(), // 180 degree DCM CLK output`
198			`.CLK270(), // 270 degree DCM CLK output`
199			`.CLK2X(), // 2X DCM CLK output`
200			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
201			`.CLK90(), // 90 degree DCM CLK output`
202			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
203			`.CLKFX(), // DCM CLK synthesis out (M/D)`
204			`.CLKFX180(), // 180 degree CLK synthesis out`
205			`.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)`
206			`.DRDY(), // Ready output signal from the DRP`
207			`.LOCKED(), // DCM LOCK status output`
208			`.PSDONE(), // Dynamic phase adjust done output`
209			`.CLKFB(CLKFB_IN), // DCM clock feedback`
210			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
211			`.DADDR(7'h00), // 7-bit address for the DRP`
212			`.DCLK(1'b0), // Clock for the DRP`
213			`.DEN(1'b0), // Enable input for the DRP`
214			`.DI(16'h0000), // 16-bit data input for the DRP`
215			`.DWE(1'b0), // Active high allows for writing configuration memory`
216			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
217			`.PSEN(1'b0), // Dynamic phase adjust enable input`
218			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
219			`.RST(1'b0) // DCM asynchronous reset input`
220			`);`
221
222			`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
223	88	rfajardo	`endif // !XILINX_FPGA
224	62	rfajardo
225
226			`endmodule`