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[/] [minsoc/] [branches/] [rc-1.0/] [sim/] [modelsim/] [compile_design.bat] - Blame information for rev 123

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Line No. Rev Author Line
1 72 rfajardo
@echo off
2 104 rfajardo
vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src
3
::vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
4 73 rfajardo
echo Finished...
5 85 rfajardo
set /p exit=Press ENTER to close this window...

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