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[/] [minsoc/] [branches/] [verilator/] [backend/] [std/] [orp.ld] - Blame information for rev 2

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Line No. Rev Author Line
1 2 rfajardo 
/*
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MEMORY
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        {
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        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
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        flash   : ORIGIN = 0x04000000, LENGTH = 0x00200000
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        ram     : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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        icm     : ORIGIN = 0x00800000, LENGTH = 0x00004000
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        }
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 */
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MEMORY
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        {
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        reset   : ORIGIN = 0x00000000, LENGTH = 0x00000200
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        vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
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    ram     : ORIGIN = 0x00001200, LENGTH = 0x00006E00  /*0x8000 total*/
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        }
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SECTIONS
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{
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        .reset :
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        {
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        *(.reset)
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        } > reset
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        .vectors :
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        {
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        _vec_start = .;
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        *(.vectors)
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        _vec_end = .;
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        } > vectors
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        .text :
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        {
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        *(.text)
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        } > ram
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      .rodata :
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        {
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        *(.rodata)
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        *(.rodata.*)
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        } > ram
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     .icm :
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        {
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        _icm_start = .;
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        *(.icm)
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        _icm_end = .;
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        } > ram
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     .data :
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        {
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        _dst_beg = .;
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        *(.data)
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        _dst_end = .;
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        } > ram
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      .bss :
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        {
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        *(.bss)
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        } > ram
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      .stack (NOLOAD) :
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        {
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        *(.stack)
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        _src_addr = .;
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        } > ram
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}

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