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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
PROJECT_SRC=(adbg_wb_biu.v
adbg_wb_module.v
adbg_or1k_module.v
adbg_wb_defines.v
adbg_defines.v
adbg_crc32.v
adbg_or1k_biu.v
adbg_or1k_defines.v
adbg_or1k_status_reg.v
adbg_top.v)

Line No.	Rev	Author	Line
1	85	rfajardo	`PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog`
2			`PROJECT_SRC=(adbg_wb_biu.v`
3			`adbg_wb_module.v`
4			`adbg_or1k_module.v`
5			`adbg_wb_defines.v`
6			`adbg_defines.v`
7			`adbg_crc32.v`
8			`adbg_or1k_biu.v`
9			`adbg_or1k_defines.v`
10			`adbg_or1k_status_reg.v`
11			`adbg_top.v)`

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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [adbg_top.prj] - Blame information for rev 147