URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [ethmac.prj] - Blame information for rev 174

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PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog
PROJECT_SRC=(eth_cop.v
eth_registers.v
eth_rxethmac.v
eth_miim.v
ethmac.v
eth_rxaddrcheck.v
eth_outputcontrol.v
eth_rxstatem.v
eth_txethmac.v
eth_wishbone.v
eth_maccontrol.v
eth_txstatem.v
ethmac_defines.v
eth_spram_256x32.v
eth_shiftreg.v
eth_clockgen.v
eth_crc.v
eth_rxcounters.v
eth_macstatus.v
eth_random.v
eth_register.v
eth_fifo.v
eth_receivecontrol.v
eth_transmitcontrol.v
eth_txcounters.v
xilinx_dist_ram_16x32.v)

Line No.	Rev	Author	Line
1	85	rfajardo	`PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog`
2			`PROJECT_SRC=(eth_cop.v`
3			`eth_registers.v`
4			`eth_rxethmac.v`
5			`eth_miim.v`
6			`ethmac.v`
7			`eth_rxaddrcheck.v`
8			`eth_outputcontrol.v`
9			`eth_rxstatem.v`
10			`eth_txethmac.v`
11			`eth_wishbone.v`
12			`eth_maccontrol.v`
13			`eth_txstatem.v`
14			`ethmac_defines.v`
15			`eth_spram_256x32.v`
16			`eth_shiftreg.v`
17			`eth_clockgen.v`
18			`eth_crc.v`
19			`eth_rxcounters.v`
20			`eth_macstatus.v`
21			`eth_random.v`
22			`eth_register.v`
23			`eth_fifo.v`
24			`eth_receivecontrol.v`
25			`eth_transmitcontrol.v`
26	120	rfajardo	`eth_txcounters.v`
27			`xilinx_dist_ram_16x32.v)`

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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [ethmac.prj] - Blame information for rev 174