OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [or1200_top.prj] - Blame information for rev 145

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 85 rfajardo 
PROJECT_DIR=rtl/verilog/or1200/rtl/verilog
2 
PROJECT_SRC=(or1200_spram_512x20.v
3 
or1200_spram_64x24.v
4 
or1200_du.v
5 
or1200_spram_2048x32_bw.v
6 
or1200_rf.v
7 
or1200_alu.v
8 
or1200_dmmu_top.v
9 
or1200_lsu.v
10 
or1200_spram_1024x32.v
11 
or1200_dc_top.v
12 
or1200_cpu.v
13 
or1200_gmultp2_32x32.v
14 
or1200_immu_top.v
15 
or1200_dpram_256x32.v
16 
or1200_tt.v
17 
or1200_iwb_biu.v
18 
or1200_rfram_generic.v
19 
or1200_dc_tag.v
20 
or1200_spram_2048x8.v
21 
or1200_immu_tlb.v
22 
or1200_ic_tag.v
23 
or1200_spram_64x14.v
24 
or1200_spram_32x24.v
25 
or1200_dpram_32x32.v
26 
or1200_xcv_ram32x8d.v
27 
or1200_spram_1024x8.v
28 
or1200_mem2reg.v
29 
or1200_pm.v
30 
or1200_spram_256x21.v
31 
or1200_operandmuxes.v
32 
or1200_pic.v
33 
or1200_cfgr.v
34 
or1200_if.v
35 
or1200_qmem_top.v
36 
or1200_genpc.v
37 
or1200_defines.v
38 
or1200_wbmux.v
39 
or1200_ic_ram.v
40 
or1200_dmmu_tlb.v
41 
or1200_sb_fifo.v
42 
or1200_sprs.v
43 
or1200_tpram_32x32.v
44 
or1200_ctrl.v
45 
or1200_sb.v
46 
or1200_mult_mac.v
47 
or1200_ic_fsm.v
48 
or1200_amultp2_32x32.v
49 
or1200_reg2mem.v
50 
or1200_spram_2048x32.v
51 
or1200_except.v
52 
or1200_top.v
53 
or1200_ic_top.v
54 
or1200_dc_ram.v
55 
or1200_spram_1024x32_bw.v
56 
or1200_freeze.v
57 
or1200_spram_128x32.v
58 
or1200_dc_fsm.v
59 
or1200_wb_biu.v
60 110 rfajardo 
or1200_spram_64x22.v)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.