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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [uart_top.prj] - Blame information for rev 174

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PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog
PROJECT_SRC=(uart_top.v
uart_sync_flops.v
uart_transmitter.v
uart_debug_if.v
uart_wb.v
uart_receiver.v
uart_tfifo.v
uart_regs.v
uart_rfifo.v
uart_defines.v
raminfr.v)

Line No.	Rev	Author	Line
1	85	rfajardo	`PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog`
2			`PROJECT_SRC=(uart_top.v`
3			`uart_sync_flops.v`
4			`uart_transmitter.v`
5			`uart_debug_if.v`
6			`uart_wb.v`
7			`uart_receiver.v`
8			`uart_tfifo.v`
9			`uart_regs.v`
10			`uart_rfifo.v`
11			`uart_defines.v`
12			`raminfr.v)`

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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [uart_top.prj] - Blame information for rev 174