URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
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rfajardo |
. ${SCRIPT_DIR}/beautify.sh
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110 |
rfajardo |
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#Configuring MinSoC
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cecho "\nConfiguring MinSoC"
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std"
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execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure"
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execcmd "cd ${DIR_TO_INSTALL}"
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#Configuring Advanced Debug System to work with MinSoC
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cecho "\nConfiguring Advanced Debug System to work with MinSoC"
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog"
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112 |
rfajardo |
execcmd "Turning off Advanced Debug System's JSP" "sed 's%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%' adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v"
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110 |
rfajardo |
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#Compiling and moving adv_jtag_bridge debug modules for simulation
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus"
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112 |
rfajardo |
execcmd "Compiling VPI interface to connect GDB with simulation" "make"
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110 |
rfajardo |
execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi"
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#Patching OpenRISC Release 1 with Advanced Debug System patch for Watchpoints
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/or1200/rtl/verilog"
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rfajardo |
cecho "Patching OpenRISC for watchpoint support"
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rfajardo |
#patch -p0 < ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Patches/OR1200v1/or1200v1_hwbkpt.patch
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patch -p0 < ${SCRIPT_DIR}/or1200v1_hwbkpt.patch
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110 |
rfajardo |
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#Precompiling firmwares
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cecho "\nPrecompiling delivered firmwares";
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/utils"
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execcmd "Make utils" "make"
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/support"
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execcmd "Make support tools" "make"
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/drivers"
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execcmd "Make drivers" "make"
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execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/uart"
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execcmd "Make UART" "make"
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