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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 9

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`include "minsoc_bench_defines.v"
`include "minsoc_defines.v"
 
module minsoc_bench();
 
reg clock, reset;
 
wire dbg_tms_i;
wire dbg_tck_i;
wire dbg_tdi_i;
wire dbg_tdo_o;
wire jtag_vref;
wire jtag_gnd;
 
wire spi_mosi;
reg spi_miso;
wire spi_sclk;
wire [1:0] spi_ss;
 
wire uart_stx;
reg uart_srx;
 
wire eth_col;
wire eth_crs;
wire eth_trst;
wire eth_tx_clk;
wire eth_tx_en;
wire eth_tx_er;
wire [3:0] eth_txd;
wire eth_rx_clk;
wire eth_rx_dv;
wire eth_rx_er;
wire [3:0] eth_rxd;
wire eth_fds_mdint;
wire eth_mdc;
wire eth_mdio;
 
//
//      TASKS registers to communicate with interfaces
//
reg [7:0] tx_data [0:1518];               //receive buffer
reg [31:0] data_in [1023:0];              //send buffer
 
 
//
// Testbench mechanics
//
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
integer initialize, final, ptr;
reg [8*64:0] file_name;
reg load_file;
 
initial begin
    reset = 1'b0;
    clock = 1'b0;
 
        load_file = 1'b0;
`ifdef INITIALIZE_MEMORY_MODEL
        load_file = 1'b1;
`endif
`ifdef START_UP
        load_file = 1'b1;
`endif
 
        //get firmware hex file from command line input
        if ( load_file ) begin
                if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
                        $display("ERROR: please specify an input file to start.");
                        $finish;
                end
                $readmemh(file_name, program_mem);
                // First word comprehends size of program
                final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
        end
 
`ifdef INITIALIZE_MEMORY_MODEL
        // Initialize memory with firmware
        initialize = 0;
        while ( initialize < final ) begin
                minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
                minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
                minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
                minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
        initialize = initialize + 4;
        end
        $display("Memory model initialized with firmware:");
        $display("%s", file_name);
        $display("%d Bytes loaded from %d ...", initialize , final);
`endif
 
    // Reset controller
    repeat (2) @ (negedge clock);
    reset = 1'b1;
    repeat (16) @ (negedge clock);
    reset = 1'b0;
 
`ifdef START_UP
        // Pass firmware over spi to or1k_startup
        ptr = 0;
        //read dummy
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        //~read dummy
        while ( ptr < final ) begin
                send_spi(program_mem[ptr]);
                ptr = ptr + 1;
        end
        $display("Memory start-up completed...");
        $display("Loaded firmware:");
        $display("%s", file_name);
`endif
        //
    // Testbench START
        //
 
 
end
 
 
//
// Modules instantiations
//
minsoc_top minsoc_top_0(
   .clk(clock),
   .reset(reset)
 
   //JTAG ports
`ifdef GENERIC_TAP
   , .jtag_tdi(dbg_tdi_i),
   .jtag_tms(dbg_tms_i),
   .jtag_tck(dbg_tck_i),
   .jtag_tdo(dbg_tdo_o),
   .jtag_vref(jtag_vref),
   .jtag_gnd(jtag_gnd)
`endif
 
   //SPI ports
`ifdef START_UP
   , .spi_flash_mosi(spi_mosi),
   .spi_flash_miso(spi_miso),
   .spi_flash_sclk(spi_sclk),
   .spi_flash_ss(spi_ss)
`endif
 
   //UART ports
`ifdef UART
   , .uart_stx(uart_stx),
   .uart_srx(uart_srx)
`endif // !UART
 
        // Ethernet ports
`ifdef ETHERNET
        , .eth_col(eth_col),
    .eth_crs(eth_crs),
    .eth_trste(eth_trst),
    .eth_tx_clk(eth_tx_clk),
        .eth_tx_en(eth_tx_en),
    .eth_tx_er(eth_tx_er),
    .eth_txd(eth_txd),
    .eth_rx_clk(eth_rx_clk),
        .eth_rx_dv(eth_rx_dv),
    .eth_rx_er(eth_rx_er),
    .eth_rxd(eth_rxd),
    .eth_fds_mdint(eth_fds_mdint),
        .eth_mdc(eth_mdc),
    .eth_mdio(eth_mdio)
`endif // !ETHERNET
);
 
`ifdef VPI_DEBUG
        dbg_comm_vpi dbg_if(
                .SYS_CLK(clock),
                .P_TMS(dbg_tms_i),
                .P_TCK(dbg_tck_i),
                .P_TRST(),
                .P_TDI(dbg_tdi_i),
                .P_TDO(dbg_tdo_o)
        );
`else
   assign dbg_tdi_i = 1;
   assign dbg_tck_i = 0;
   assign dbg_tms_i = 1;
`endif
 
`ifdef ETHERNET
eth_phy my_phy // This PHY model simulate simplified Intel LXT971A PHY
(
          // COMMON
          .m_rst_n_i(1'b1),
 
          // MAC TX
          .mtx_clk_o(eth_tx_clk),
          .mtxd_i(eth_txd),
          .mtxen_i(eth_tx_en),
          .mtxerr_i(eth_tx_er),
 
          // MAC RX
          .mrx_clk_o(eth_rx_clk),
          .mrxd_o(eth_rxd),
          .mrxdv_o(eth_rx_dv),
          .mrxerr_o(eth_rx_er),
 
          .mcoll_o(eth_col),
          .mcrs_o(eth_crs),
 
          // MIIM
          .mdc_i(eth_mdc),
          .md_io(eth_mdio),
 
          // SYSTEM
          .phy_log()
);
`endif // !ETHERNET
 
 
//
//      Regular clocking and output
//
always begin
    #((`CLK_PERIOD)/2) clock <= ~clock;
end
 
`ifdef VCD_OUTPUT
initial begin
        $dumpfile("../results/minsoc_wave.vcd");
        $dumpvars();
end
`endif
 
 
//
//      Functionalities tasks: SPI Startup and UART Monitor
//
//SPI START_UP
`ifdef START_UP
task send_spi;
    input [7:0] data_in;
    integer i;
    begin
        i = 7;
        for ( i = 7 ; i >= 0; i = i - 1 ) begin
                spi_miso = data_in[i];
                        @ (posedge spi_sclk);
            end
    end
endtask
`endif
//~SPI START_UP
 
//UART Monitor (prints uart output on the terminal)
`ifdef UART
parameter UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD;
 
// Something to trigger the task
always @(posedge clock)
        uart_decoder;
 
task uart_decoder;
        integer i;
        reg [7:0] tx_byte;
        begin
 
        // Wait for start bit
        while (uart_stx == 1'b1)
                @(uart_stx);
 
        #(UART_TX_WAIT+(UART_TX_WAIT/2));
 
    for ( i = 0; i < 8 ; i = i + 1 ) begin
                tx_byte[i] = uart_stx;
                #UART_TX_WAIT;
        end
 
        //Check for stop bit
        if (uart_stx == 1'b0) begin
                  //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
          // Wait for return to idle
                while (uart_stx == 1'b0)
                        @(uart_stx);
          //$display("* USER UART returned to idle at time %d",$time);
        end
        // display the char
        $write("%c", tx_byte);
        end
endtask
`endif // !UART
//~UART Monitor
 
 
//
//      TASKS to communicate with interfaces
//
//MAC_DATA
//
`ifdef ETHERNET
reg [31:0] crc32_result;
 
task get_mac;
    integer conta;
    reg LSB;
    begin
        conta = 0;
        LSB = 1;
        @ ( posedge eth_tx_en);
        while ( eth_tx_en == 1'b1 ) begin
            @ (negedge eth_tx_clk) begin
                if ( LSB == 1'b1 )
                    tx_data[conta][3:0] = eth_txd;
                else begin
                    tx_data[conta][7:4] = eth_txd;
                    conta = conta + 1;
                end
                LSB = ~LSB;
            end
        end
    end
endtask
 
task send_mac;
    input [11:0] command;
    input [31:0] param1;
    input [31:0] param2;
    input [223:0] data;
 
    integer conta;
 
    begin
        //DEST MAC
        my_phy.rx_mem[0] = 8'h55;
        my_phy.rx_mem[1] = 8'h47;
        my_phy.rx_mem[2] = 8'h34;
        my_phy.rx_mem[3] = 8'h22;
        my_phy.rx_mem[4] = 8'h88;
        my_phy.rx_mem[5] = 8'h92;
 
        //SOURCE MAC
        my_phy.rx_mem[6] = 8'h00;
        my_phy.rx_mem[7] = 8'h00;
        my_phy.rx_mem[8] = 8'hC0;
        my_phy.rx_mem[9] = 8'h41;
        my_phy.rx_mem[10] = 8'h36;
        my_phy.rx_mem[11] = 8'hD3;
 
        //LEN
        my_phy.rx_mem[12] = 8'h00;
        my_phy.rx_mem[13] = 8'h04;
 
        //DATA
        my_phy.rx_mem[14] = 8'hFF;
        my_phy.rx_mem[15] = 8'hFA;
        my_phy.rx_mem[16] = command[11:4];
        my_phy.rx_mem[17] = { command[3:0] , 4'h7 };
 
        my_phy.rx_mem[18] = 8'hAA;
        my_phy.rx_mem[19] = 8'hAA;
 
        //parameter 1
        my_phy.rx_mem[20] = param1[31:24];
        my_phy.rx_mem[21] = param1[23:16];
        my_phy.rx_mem[22] = param1[15:8];
        my_phy.rx_mem[23] = param1[7:0];
 
        //parameter 2
        my_phy.rx_mem[24] = param2[31:24];
        my_phy.rx_mem[25] = param2[23:16];
        my_phy.rx_mem[26] = param2[15:8];
        my_phy.rx_mem[27] = param2[7:0];
 
        //data
        my_phy.rx_mem[28] = data[223:216];
        my_phy.rx_mem[29] = data[215:208];
        my_phy.rx_mem[30] = data[207:200];
        my_phy.rx_mem[31] = data[199:192];
        my_phy.rx_mem[32] = data[191:184];
        my_phy.rx_mem[33] = data[183:176];
        my_phy.rx_mem[34] = data[175:168];
        my_phy.rx_mem[35] = data[167:160];
        my_phy.rx_mem[36] = data[159:152];
        my_phy.rx_mem[37] = data[151:144];
        my_phy.rx_mem[38] = data[143:136];
        my_phy.rx_mem[39] = data[135:128];
        my_phy.rx_mem[40] = data[127:120];
        my_phy.rx_mem[41] = data[119:112];
        my_phy.rx_mem[42] = data[111:104];
        my_phy.rx_mem[43] = data[103:96];
        my_phy.rx_mem[44] = data[95:88];
        my_phy.rx_mem[45] = data[87:80];
        my_phy.rx_mem[46] = data[79:72];
        my_phy.rx_mem[47] = data[71:64];
        my_phy.rx_mem[48] = data[63:56];
        my_phy.rx_mem[49] = data[55:48];
        my_phy.rx_mem[50] = data[47:40];
        my_phy.rx_mem[51] = data[39:32];
        my_phy.rx_mem[52] = data[31:24];
        my_phy.rx_mem[53] = data[23:16];
        my_phy.rx_mem[54] = data[15:8];
        my_phy.rx_mem[55] = data[7:0];
 
        //PAD
        for ( conta = 56; conta < 60; conta = conta + 1 ) begin
            my_phy.rx_mem[conta] = 8'h00;
        end
 
        gencrc32;
 
        my_phy.rx_mem[60] = crc32_result[31:24];
        my_phy.rx_mem[61] = crc32_result[23:16];
        my_phy.rx_mem[62] = crc32_result[15:8];
        my_phy.rx_mem[63] = crc32_result[7:0];
 
        my_phy.send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, 32'h0000_0040, 1'b0 );
    end
 
endtask
 
//CRC32
parameter [31:0] CRC32_POLY = 32'h04C11DB7;
 
task gencrc32;
    integer     byte, bit;
    reg         msb;
    reg [7:0]    current_byte;
    reg [31:0]   temp;
 
    integer crc32_length;
 
    begin
        crc32_length = 60;
        crc32_result = 32'hffffffff;
        for (byte = 0; byte < crc32_length; byte = byte + 1) begin
            current_byte = my_phy.rx_mem[byte];
            for (bit = 0; bit < 8; bit = bit + 1) begin
                msb = crc32_result[31];
                crc32_result = crc32_result << 1;
                if (msb != current_byte[bit]) begin
                    crc32_result = crc32_result ^ CRC32_POLY;
                    crc32_result[0] = 1;
                end
            end
        end
 
        // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
        //
        // Mirror:
        for (bit = 0; bit < 32; bit = bit + 1)
            temp[31-bit] = crc32_result[bit];
 
        // Swap and Complement:
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
    end
endtask
//~CRC32
`endif // !ETHERNET
//~MAC_DATA
 
 
endmodule
 

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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	2	rfajardo	`include "minsoc_bench_defines.v"
2			`include "minsoc_defines.v"
3
4			`module minsoc_bench();`
5
6			`reg clock, reset;`
7
8			`wire dbg_tms_i;`
9			`wire dbg_tck_i;`
10			`wire dbg_tdi_i;`
11			`wire dbg_tdo_o;`
12			`wire jtag_vref;`
13			`wire jtag_gnd;`
14
15			`wire spi_mosi;`
16			`reg spi_miso;`
17			`wire spi_sclk;`
18			`wire [1:0] spi_ss;`
19
20			`wire uart_stx;`
21	9	rfajardo	`reg uart_srx;`
22	2	rfajardo
23			`wire eth_col;`
24			`wire eth_crs;`
25			`wire eth_trst;`
26			`wire eth_tx_clk;`
27			`wire eth_tx_en;`
28			`wire eth_tx_er;`
29			`wire [3:0] eth_txd;`
30			`wire eth_rx_clk;`
31			`wire eth_rx_dv;`
32			`wire eth_rx_er;`
33			`wire [3:0] eth_rxd;`
34			`wire eth_fds_mdint;`
35			`wire eth_mdc;`
36			`wire eth_mdio;`
37
38			`//`
39			`// TASKS registers to communicate with interfaces`
40			`//`
41			`reg [7:0] tx_data [0:1518]; //receive buffer`
42			`reg [31:0] data_in [1023:0]; //send buffer`
43
44
45			`//`
46			`// Testbench mechanics`
47			`//`
48	4	rfajardo	reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
49	2	rfajardo	`integer initialize, final, ptr;`
50			`reg [8*64:0] file_name;`
51			`reg load_file;`
52	8	rfajardo
53	2	rfajardo	`initial begin`
54	8	rfajardo	`reset = 1'b0;`
55			`clock = 1'b0;`
56
57	2	rfajardo	`load_file = 1'b0;`
58			`ifdef INITIALIZE_MEMORY_MODEL
59			`load_file = 1'b1;`
60			`endif
61			`ifdef START_UP
62			`load_file = 1'b1;`
63			`endif
64	8	rfajardo
65	2	rfajardo	`//get firmware hex file from command line input`
66			`if ( load_file ) begin`
67			`if ( ! $value$plusargs("file_name=%s", file_name) \|\| file_name == 0 ) begin`
68			`$display("ERROR: please specify an input file to start.");`
69			`$finish;`
70			`end`
71			`$readmemh(file_name, program_mem);`
72			`// First word comprehends size of program`
73			`final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };`
74			`end`
75
76			`ifdef INITIALIZE_MEMORY_MODEL
77			`// Initialize memory with firmware`
78			`initialize = 0;`
79			`while ( initialize < final ) begin`
80			`minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];`
81			`minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];`
82			`minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];`
83			`minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];`
84			`initialize = initialize + 4;`
85			`end`
86			`$display("Memory model initialized with firmware:");`
87			`$display("%s", file_name);`
88			`$display("%d Bytes loaded from %d ...", initialize , final);`
89			`endif
90
91			`// Reset controller`
92			`repeat (2) @ (negedge clock);`
93			`reset = 1'b1;`
94			`repeat (16) @ (negedge clock);`
95			`reset = 1'b0;`
96
97			`ifdef START_UP
98			`// Pass firmware over spi to or1k_startup`
99			`ptr = 0;`
100			`//read dummy`
101			`send_spi(program_mem[ptr]);`
102			`send_spi(program_mem[ptr]);`
103			`send_spi(program_mem[ptr]);`
104			`send_spi(program_mem[ptr]);`
105			`//~read dummy`
106			`while ( ptr < final ) begin`
107			`send_spi(program_mem[ptr]);`
108			`ptr = ptr + 1;`
109			`end`
110			`$display("Memory start-up completed...");`
111			`$display("Loaded firmware:");`
112			`$display("%s", file_name);`
113			`endif
114			`//`
115			`// Testbench START`
116			`//`
117
118
119			`end`
120
121
122			`//`
123			`// Modules instantiations`
124			`//`
125			`minsoc_top minsoc_top_0(`
126			`.clk(clock),`
127			`.reset(reset)`
128
129			`//JTAG ports`
130			`ifdef GENERIC_TAP
131			`, .jtag_tdi(dbg_tdi_i),`
132			`.jtag_tms(dbg_tms_i),`
133			`.jtag_tck(dbg_tck_i),`
134			`.jtag_tdo(dbg_tdo_o),`
135			`.jtag_vref(jtag_vref),`
136			`.jtag_gnd(jtag_gnd)`
137			`endif
138
139			`//SPI ports`
140			`ifdef START_UP
141			`, .spi_flash_mosi(spi_mosi),`
142			`.spi_flash_miso(spi_miso),`
143			`.spi_flash_sclk(spi_sclk),`
144			`.spi_flash_ss(spi_ss)`
145			`endif
146
147			`//UART ports`
148			`ifdef UART
149			`, .uart_stx(uart_stx),`
150			`.uart_srx(uart_srx)`
151			`endif // !UART
152
153			`// Ethernet ports`
154			`ifdef ETHERNET
155			`, .eth_col(eth_col),`
156			`.eth_crs(eth_crs),`
157			`.eth_trste(eth_trst),`
158			`.eth_tx_clk(eth_tx_clk),`
159			`.eth_tx_en(eth_tx_en),`
160			`.eth_tx_er(eth_tx_er),`
161			`.eth_txd(eth_txd),`
162			`.eth_rx_clk(eth_rx_clk),`
163			`.eth_rx_dv(eth_rx_dv),`
164			`.eth_rx_er(eth_rx_er),`
165			`.eth_rxd(eth_rxd),`
166			`.eth_fds_mdint(eth_fds_mdint),`
167			`.eth_mdc(eth_mdc),`
168			`.eth_mdio(eth_mdio)`
169			`endif // !ETHERNET
170			`);`
171
172			`ifdef VPI_DEBUG
173			`dbg_comm_vpi dbg_if(`
174			`.SYS_CLK(clock),`
175			`.P_TMS(dbg_tms_i),`
176			`.P_TCK(dbg_tck_i),`
177			`.P_TRST(),`
178			`.P_TDI(dbg_tdi_i),`
179			`.P_TDO(dbg_tdo_o)`
180			`);`
181			`else
182			`assign dbg_tdi_i = 1;`
183			`assign dbg_tck_i = 0;`
184			`assign dbg_tms_i = 1;`
185			`endif
186
187			`ifdef ETHERNET
188			`eth_phy my_phy // This PHY model simulate simplified Intel LXT971A PHY`
189			`(`
190			`// COMMON`
191			`.m_rst_n_i(1'b1),`
192
193			`// MAC TX`
194			`.mtx_clk_o(eth_tx_clk),`
195			`.mtxd_i(eth_txd),`
196			`.mtxen_i(eth_tx_en),`
197			`.mtxerr_i(eth_tx_er),`
198
199			`// MAC RX`
200			`.mrx_clk_o(eth_rx_clk),`
201			`.mrxd_o(eth_rxd),`
202			`.mrxdv_o(eth_rx_dv),`
203			`.mrxerr_o(eth_rx_er),`
204
205			`.mcoll_o(eth_col),`
206			`.mcrs_o(eth_crs),`
207
208			`// MIIM`
209			`.mdc_i(eth_mdc),`
210			`.md_io(eth_mdio),`
211
212			`// SYSTEM`
213			`.phy_log()`
214			`);`
215			`endif // !ETHERNET
216
217
218			`//`
219	8	rfajardo	`// Regular clocking and output`
220	2	rfajardo	`//`
221			`always begin`
222			#((`CLK_PERIOD)/2) clock <= ~clock;
223			`end`
224
225			`ifdef VCD_OUTPUT
226			`initial begin`
227			`$dumpfile("../results/minsoc_wave.vcd");`
228			`$dumpvars();`
229			`end`
230			`endif
231
232
233			`//`
234			`// Functionalities tasks: SPI Startup and UART Monitor`
235			`//`
236			`//SPI START_UP`
237			`ifdef START_UP
238			`task send_spi;`
239			`input [7:0] data_in;`
240			`integer i;`
241			`begin`
242			`i = 7;`
243			`for ( i = 7 ; i >= 0; i = i - 1 ) begin`
244			`spi_miso = data_in[i];`
245			`@ (posedge spi_sclk);`
246			`end`
247			`end`
248			`endtask`
249			`endif
250			`//~SPI START_UP`
251
252			`//UART Monitor (prints uart output on the terminal)`
253			`ifdef UART
254			parameter UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD;
255
256			`// Something to trigger the task`
257			`always @(posedge clock)`
258			`uart_decoder;`
259
260			`task uart_decoder;`
261			`integer i;`
262			`reg [7:0] tx_byte;`
263			`begin`
264
265			`// Wait for start bit`
266			`while (uart_stx == 1'b1)`
267			`@(uart_stx);`
268
269			`#(UART_TX_WAIT+(UART_TX_WAIT/2));`
270
271			`for ( i = 0; i < 8 ; i = i + 1 ) begin`
272			`tx_byte[i] = uart_stx;`
273			`#UART_TX_WAIT;`
274			`end`
275
276			`//Check for stop bit`
277			`if (uart_stx == 1'b0) begin`
278			`//$display("* WARNING: user stop bit not received when expected at time %d__", $time);`
279			`// Wait for return to idle`
280			`while (uart_stx == 1'b0)`
281			`@(uart_stx);`
282			`//$display("* USER UART returned to idle at time %d",$time);`
283			`end`
284			`// display the char`
285			`$write("%c", tx_byte);`
286			`end`
287			`endtask`
288			`endif // !UART
289			`//~UART Monitor`
290
291
292			`//`
293			`// TASKS to communicate with interfaces`
294			`//`
295			`//MAC_DATA`
296			`//`
297			`ifdef ETHERNET
298			`reg [31:0] crc32_result;`
299
300			`task get_mac;`
301			`integer conta;`
302			`reg LSB;`
303			`begin`
304			`conta = 0;`
305			`LSB = 1;`
306			`@ ( posedge eth_tx_en);`
307			`while ( eth_tx_en == 1'b1 ) begin`
308			`@ (negedge eth_tx_clk) begin`
309			`if ( LSB == 1'b1 )`
310			`tx_data[conta][3:0] = eth_txd;`
311			`else begin`
312			`tx_data[conta][7:4] = eth_txd;`
313			`conta = conta + 1;`
314			`end`
315			`LSB = ~LSB;`
316			`end`
317			`end`
318			`end`
319			`endtask`
320
321			`task send_mac;`
322			`input [11:0] command;`
323			`input [31:0] param1;`
324			`input [31:0] param2;`
325			`input [223:0] data;`
326
327			`integer conta;`
328
329			`begin`
330			`//DEST MAC`
331			`my_phy.rx_mem[0] = 8'h55;`
332			`my_phy.rx_mem[1] = 8'h47;`
333			`my_phy.rx_mem[2] = 8'h34;`
334			`my_phy.rx_mem[3] = 8'h22;`
335			`my_phy.rx_mem[4] = 8'h88;`
336			`my_phy.rx_mem[5] = 8'h92;`
337
338			`//SOURCE MAC`
339			`my_phy.rx_mem[6] = 8'h00;`
340			`my_phy.rx_mem[7] = 8'h00;`
341			`my_phy.rx_mem[8] = 8'hC0;`
342			`my_phy.rx_mem[9] = 8'h41;`
343			`my_phy.rx_mem[10] = 8'h36;`
344			`my_phy.rx_mem[11] = 8'hD3;`
345
346			`//LEN`
347			`my_phy.rx_mem[12] = 8'h00;`
348			`my_phy.rx_mem[13] = 8'h04;`
349
350			`//DATA`
351			`my_phy.rx_mem[14] = 8'hFF;`
352			`my_phy.rx_mem[15] = 8'hFA;`
353			`my_phy.rx_mem[16] = command[11:4];`
354			`my_phy.rx_mem[17] = { command[3:0] , 4'h7 };`
355
356			`my_phy.rx_mem[18] = 8'hAA;`
357			`my_phy.rx_mem[19] = 8'hAA;`
358
359			`//parameter 1`
360			`my_phy.rx_mem[20] = param1[31:24];`
361			`my_phy.rx_mem[21] = param1[23:16];`
362			`my_phy.rx_mem[22] = param1[15:8];`
363			`my_phy.rx_mem[23] = param1[7:0];`
364
365			`//parameter 2`
366			`my_phy.rx_mem[24] = param2[31:24];`
367			`my_phy.rx_mem[25] = param2[23:16];`
368			`my_phy.rx_mem[26] = param2[15:8];`
369			`my_phy.rx_mem[27] = param2[7:0];`
370
371			`//data`
372			`my_phy.rx_mem[28] = data[223:216];`
373			`my_phy.rx_mem[29] = data[215:208];`
374			`my_phy.rx_mem[30] = data[207:200];`
375			`my_phy.rx_mem[31] = data[199:192];`
376			`my_phy.rx_mem[32] = data[191:184];`
377			`my_phy.rx_mem[33] = data[183:176];`
378			`my_phy.rx_mem[34] = data[175:168];`
379			`my_phy.rx_mem[35] = data[167:160];`
380			`my_phy.rx_mem[36] = data[159:152];`
381			`my_phy.rx_mem[37] = data[151:144];`
382			`my_phy.rx_mem[38] = data[143:136];`
383			`my_phy.rx_mem[39] = data[135:128];`
384			`my_phy.rx_mem[40] = data[127:120];`
385			`my_phy.rx_mem[41] = data[119:112];`
386			`my_phy.rx_mem[42] = data[111:104];`
387			`my_phy.rx_mem[43] = data[103:96];`
388			`my_phy.rx_mem[44] = data[95:88];`
389			`my_phy.rx_mem[45] = data[87:80];`
390			`my_phy.rx_mem[46] = data[79:72];`
391			`my_phy.rx_mem[47] = data[71:64];`
392			`my_phy.rx_mem[48] = data[63:56];`
393			`my_phy.rx_mem[49] = data[55:48];`
394			`my_phy.rx_mem[50] = data[47:40];`
395			`my_phy.rx_mem[51] = data[39:32];`
396			`my_phy.rx_mem[52] = data[31:24];`
397			`my_phy.rx_mem[53] = data[23:16];`
398			`my_phy.rx_mem[54] = data[15:8];`
399			`my_phy.rx_mem[55] = data[7:0];`
400
401			`//PAD`
402			`for ( conta = 56; conta < 60; conta = conta + 1 ) begin`
403			`my_phy.rx_mem[conta] = 8'h00;`
404			`end`
405
406			`gencrc32;`
407
408			`my_phy.rx_mem[60] = crc32_result[31:24];`
409			`my_phy.rx_mem[61] = crc32_result[23:16];`
410			`my_phy.rx_mem[62] = crc32_result[15:8];`
411			`my_phy.rx_mem[63] = crc32_result[7:0];`
412
413			`my_phy.send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, 32'h0000_0040, 1'b0 );`
414			`end`
415
416			`endtask`
417
418			`//CRC32`
419			`parameter [31:0] CRC32_POLY = 32'h04C11DB7;`
420
421			`task gencrc32;`
422			`integer byte, bit;`
423			`reg msb;`
424			`reg [7:0] current_byte;`
425			`reg [31:0] temp;`
426
427			`integer crc32_length;`
428
429			`begin`
430			`crc32_length = 60;`
431			`crc32_result = 32'hffffffff;`
432			`for (byte = 0; byte < crc32_length; byte = byte + 1) begin`
433			`current_byte = my_phy.rx_mem[byte];`
434			`for (bit = 0; bit < 8; bit = bit + 1) begin`
435			`msb = crc32_result[31];`
436			`crc32_result = crc32_result << 1;`
437			`if (msb != current_byte[bit]) begin`
438			`crc32_result = crc32_result ^ CRC32_POLY;`
439			`crc32_result[0] = 1;`
440			`end`
441			`end`
442			`end`
443
444			`// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.`
445			`//`
446			`// Mirror:`
447			`for (bit = 0; bit < 32; bit = bit + 1)`
448			`temp[31-bit] = crc32_result[bit];`
449
450			`// Swap and Complement:`
451			`crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};`
452			`end`
453			`endtask`
454			`//~CRC32`
455			`endif // !ETHERNET
456			`//~MAC_DATA`
457
458
459			`endmodule`
460