OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [spartan3a_dsp_kit/] [spartan3a_dsp_kit.ucf] - Blame information for rev 122

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 rfajardo
###########################
2
##
3
## Global signals
4
##
5 2 rfajardo
net "clk" loc = "f13";                                          #125MHz clock
6 63 rfajardo
net "reset" loc = "j17";                                        #SW5
7
###########################
8
 
9
###########################
10
##
11
## JTAG
12
##
13 15 rfajardo
#net "jtag_tms" loc = "aa23";                                   #SAM D0
14
#net "jtag_tdi" loc = "u20";                                    #SAM D2
15
#net "jtag_tdo" loc = "aa25";                                           #SAM D4
16
#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE;    #SAM D6
17
#net "jtag_gnd" loc = "y23";                                    #SAM D8
18 63 rfajardo
#net "jtag_vref" loc = "t20";                                   #SAM D10
19
###########################
20
 
21
#############################
22
##
23
## SPI Flash External Memory
24
##
25 67 rfajardo
#NET "spi_flash_mosi" LOC = "ab15";
26
#NET "spi_flash_miso" LOC = "af24";
27
#NET "spi_flash_sclk" LOC = "ae24";
28
#NET "spi_flash_ss(1)" LOC = "ac25";
29
#NET "spi_flash_ss(0)" LOC = "aa7";
30 63 rfajardo
###########################
31
 
32
###########################
33
##
34
## UART
35
##
36
net "uart_stx" loc = "p22";
37
net "uart_srx" loc = "n21";
38
###########################
39
 
40
###########################
41
##
42
## ETH
43
##
44 64 rfajardo
NET "eth_txd(3)" LOC = "b1";
45
NET "eth_txd(2)" LOC = "b2";
46
NET "eth_txd(1)" LOC = "j9";
47
NET "eth_txd(0)" LOC = "j8";
48
 
49
NET "eth_tx_en" LOC = "d3";
50
NET "eth_tx_clk" LOC = "p2";
51
NET "eth_tx_er" LOC = "e4";
52
 
53
NET "eth_rxd(3)" LOC = "d2";
54
NET "eth_rxd(2)" LOC = "g5";
55
NET "eth_rxd(1)" LOC = "g2";
56
NET "eth_rxd(0)" LOC = "c2";
57
 
58
NET "eth_rx_er" LOC = "j3";
59
NET "eth_rx_dv" LOC = "d1";
60
 
61
NET "eth_rx_clk" LOC = "p1";
62
 
63
NET "eth_mdio" LOC = "f5" | PULLUP;
64
NET "eth_crs" LOC = "g1";
65
NET "eth_col" LOC = "y3";
66
NET "eth_mdc" LOC = "f4";
67
 
68
NET "eth_trste" LOC = "g4";
69
 
70
NET "eth_fds_mdint" LOC = "j1";
71 63 rfajardo
###########################
72
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.