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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Blame information for rev 139

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////         Wishbone Single-Port Synchronous RAM                                 ////
////                    Memory Model                                      ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/minsoc/                       ////
////                                                              ////
////  Description                                                 ////
////  This Wishbone controller connects to the wrapper of         ////
////  the single-port synchronous memory interface.               ////
////  Besides universal memory due to onchip_ram it provides a    ////
////  generic way to set the depth of the memory.                 ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Raul Fajardo, rfajardo@gmail.com                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.gnu.org/licenses/lgpl.html                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Created interface and tested
//
 
`include "timescale.v"
 
module minsoc_memory_model (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o
);
 
// 
// Parameters 
//
parameter    adr_width = 2;
 
// 
// I/O Ports 
// 
input      wb_clk_i;
input      wb_rst_i;
 
// 
// WB slave i/f 
// 
input  [31:0]   wb_dat_i;
output [31:0]   wb_dat_o;
input  [31:0]   wb_adr_i;
input  [3:0]    wb_sel_i;
input      wb_we_i;
input      wb_cyc_i;
input      wb_stb_i;
output     wb_ack_o;
output     wb_err_o;
 
// 
// Internal regs and wires 
// 
wire    we;
wire [3:0]  be_i;
wire [31:0]  wb_dat_o;
reg    ack_we;
reg    ack_re;
// 
// Aliases and simple assignments 
// 
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);  // If Access to > (8-bit leading prefix ignored) 
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
 
// 
// Write acknowledge 
// 
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
// 
// read acknowledge 
// 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_re <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
    ack_re <= #1 1'b1;
  else
    ack_re <= #1 1'b0;
end
 
    minsoc_onchip_ram #
        (
                .aw(adr_width)
        )
        block_ram_0 (
        .clk(wb_clk_i),
        .rst(wb_rst_i),
        .addr(wb_adr_i[adr_width+1:2]),
        .di(wb_dat_i[7:0]),
        .doq(wb_dat_o[7:0]),
        .we(we),
        .oe(1'b1),
        .ce(be_i[0]));
 
    minsoc_onchip_ram #
        (
                .aw(adr_width)
        )
        block_ram_1 (
        .clk(wb_clk_i),
        .rst(wb_rst_i),
        .addr(wb_adr_i[adr_width+1:2]),
        .di(wb_dat_i[15:8]),
        .doq(wb_dat_o[15:8]),
        .we(we),
        .oe(1'b1),
        .ce(be_i[1]));
 
    minsoc_onchip_ram #
        (
                .aw(adr_width)
        )
        block_ram_2 (
        .clk(wb_clk_i),
        .rst(wb_rst_i),
        .addr(wb_adr_i[adr_width+1:2]),
        .di(wb_dat_i[23:16]),
        .doq(wb_dat_o[23:16]),
        .we(we),
        .oe(1'b1),
        .ce(be_i[2]));
 
    minsoc_onchip_ram #
        (
                .aw(adr_width)
        )
        block_ram_3 (
        .clk(wb_clk_i),
        .rst(wb_rst_i),
        .addr(wb_adr_i[adr_width+1:2]),
        .di(wb_dat_i[31:24]),
        .doq(wb_dat_o[31:24]),
        .we(we),
        .oe(1'b1),
        .ce(be_i[3]));
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rfajardo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Wishbone Single-Port Synchronous RAM ////`
4			`//// Memory Model ////`
5			`//// ////`
6			`//// This file is part of memory library available from ////`
7			`//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// This Wishbone controller connects to the wrapper of ////`
11			`//// the single-port synchronous memory interface. ////`
12			`//// Besides universal memory due to onchip_ram it provides a ////`
13			`//// generic way to set the depth of the memory. ////`
14			`//// ////`
15			`//// To Do: ////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Raul Fajardo, rfajardo@gmail.com ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.gnu.org/licenses/lgpl.html ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// Revision History`
48			`//`
49			`//`
50			`// Revision 1.0 2009/08/18 15:15:00 fajardo`
51			`// Created interface and tested`
52			`//`
53
54	71	rfajardo	`include "timescale.v"
55	2	rfajardo
56	60	rfajardo	`module minsoc_memory_model (`
57	2	rfajardo	`wb_clk_i, wb_rst_i,`
58
59			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
60			`wb_stb_i, wb_ack_o, wb_err_o`
61			`);`
62
63			`//`
64			`// Parameters`
65			`//`
66			`parameter adr_width = 2;`
67
68			`//`
69			`// I/O Ports`
70			`//`
71			`input wb_clk_i;`
72			`input wb_rst_i;`
73
74			`//`
75			`// WB slave i/f`
76			`//`
77			`input [31:0] wb_dat_i;`
78			`output [31:0] wb_dat_o;`
79			`input [31:0] wb_adr_i;`
80			`input [3:0] wb_sel_i;`
81			`input wb_we_i;`
82			`input wb_cyc_i;`
83			`input wb_stb_i;`
84			`output wb_ack_o;`
85			`output wb_err_o;`
86
87			`//`
88			`// Internal regs and wires`
89			`//`
90			`wire we;`
91			`wire [3:0] be_i;`
92			`wire [31:0] wb_dat_o;`
93			`reg ack_we;`
94			`reg ack_re;`
95			`//`
96			`// Aliases and simple assignments`
97			`//`
98			`assign wb_ack_o = ack_re \| ack_we;`
99			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)`
100			`assign we = wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:0]);`
101			`assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;`
102
103			`//`
104			`// Write acknowledge`
105			`//`
106			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
107			`begin`
108			`if (wb_rst_i)`
109			`ack_we <= 1'b0;`
110			`else`
111			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
112			`ack_we <= #1 1'b1;`
113			`else`
114			`ack_we <= #1 1'b0;`
115			`end`
116
117			`//`
118			`// read acknowledge`
119			`//`
120			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
121			`begin`
122			`if (wb_rst_i)`
123			`ack_re <= 1'b0;`
124			`else`
125			`if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)`
126			`ack_re <= #1 1'b1;`
127			`else`
128			`ack_re <= #1 1'b0;`
129			`end`
130
131			`minsoc_onchip_ram #`
132			`(`
133			`.aw(adr_width)`
134			`)`
135			`block_ram_0 (`
136			`.clk(wb_clk_i),`
137			`.rst(wb_rst_i),`
138			`.addr(wb_adr_i[adr_width+1:2]),`
139			`.di(wb_dat_i[7:0]),`
140			`.doq(wb_dat_o[7:0]),`
141			`.we(we),`
142			`.oe(1'b1),`
143			`.ce(be_i[0]));`
144
145			`minsoc_onchip_ram #`
146			`(`
147			`.aw(adr_width)`
148			`)`
149			`block_ram_1 (`
150			`.clk(wb_clk_i),`
151			`.rst(wb_rst_i),`
152			`.addr(wb_adr_i[adr_width+1:2]),`
153			`.di(wb_dat_i[15:8]),`
154			`.doq(wb_dat_o[15:8]),`
155			`.we(we),`
156			`.oe(1'b1),`
157			`.ce(be_i[1]));`
158
159			`minsoc_onchip_ram #`
160			`(`
161			`.aw(adr_width)`
162			`)`
163			`block_ram_2 (`
164			`.clk(wb_clk_i),`
165			`.rst(wb_rst_i),`
166			`.addr(wb_adr_i[adr_width+1:2]),`
167			`.di(wb_dat_i[23:16]),`
168			`.doq(wb_dat_o[23:16]),`
169			`.we(we),`
170			`.oe(1'b1),`
171			`.ce(be_i[2]));`
172
173			`minsoc_onchip_ram #`
174			`(`
175			`.aw(adr_width)`
176			`)`
177			`block_ram_3 (`
178			`.clk(wb_clk_i),`
179			`.rst(wb_rst_i),`
180			`.addr(wb_adr_i[adr_width+1:2]),`
181			`.di(wb_dat_i[31:24]),`
182			`.doq(wb_dat_o[31:24]),`
183			`.we(we),`
184			`.oe(1'b1),`
185			`.ce(be_i[3]));`
186
187			`endmodule`
188

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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Blame information for rev 139