OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Blame information for rev 105

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  dbg_comm_vpi.v                                              ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the SoC/OpenRISC Development Interface ////
7
////  http://www.opencores.org/cores/DebugInterface/              ////
8
////                                                              ////
9
////                                                              ////
10
////  Author(s):                                                  ////
11
////       Igor Mohor (igorm@opencores.org)                       ////
12
////       Gyorgy Jeney (nog@sdf.lonestar.net)                    ////
13
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
14
////       Raul Fajardo (rfajardo@gmail.com)                                      ////
15
////                                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000-2008 Authors                              ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: dbg_comm_vpi.v,v $
47
// Revision 1.2.1  2009/09/08 14:57  rfajardo
48
// Changed clock and reset outputs to inputs for minsoc
49
//
50
// $Log: dbg_comm_vpi.v,v $
51
// Revision 1.2  2009/05/17 20:55:57  Nathan
52
// Changed email address to opencores.org
53
//
54
// Revision 1.1  2008/07/26 17:33:20  Nathan
55
// Added debug comm module for use with VPI / network communication.
56
//
57
// Revision 1.1  2002/03/28 19:59:54  lampret
58
// Added bench directory
59
//
60
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
61
// First import.
62
//
63
// Revision 1.3  2001/09/24 14:06:13  mohor
64
// Changes connected to the OpenRISC access (SPR read, SPR write).
65
//
66
// Revision 1.2  2001/09/20 10:10:30  mohor
67
// Working version. Few bugs fixed, comments added.
68
//
69
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
70
// Initial official release.
71
//
72
//
73
//
74
//
75
//
76
 
77 71 rfajardo
`include "timescale.v"
78 2 rfajardo
 
79
`define JP_PORT "4567"
80
`define TIMEOUT_COUNT 6'd20  // 1/2 of a TCK clock will be this many SYS_CLK ticks.  Must be less than 6 bits. 
81
 
82
  module dbg_comm_vpi (
83
                       SYS_CLK,
84
                       P_TMS,
85
                       P_TCK,
86
                       P_TRST,
87
                       P_TDI,
88
                       P_TDO
89
                       );
90
 
91
   //parameter Tp = 20;
92
 
93
   input     SYS_CLK;
94
   output    P_TMS;
95
   output    P_TCK;
96
   output    P_TRST;
97
   output    P_TDI;
98
   input     P_TDO;
99
 
100
 
101
   reg [4:0] memory;  // [0:0];
102
 
103
 
104
   wire      P_TCK;
105
   wire      P_TRST;
106
   wire      P_TDI;
107
   wire      P_TMS;
108
   wire      P_TDO;
109
 
110
   reg [3:0] in_word_r;
111
   reg [5:0] clk_count;
112
 
113
 
114
   // Handle commands from the upper level
115
   initial
116
     begin
117
        in_word_r = 5'b0;
118
        memory = 5'b0;
119
        $jp_init(`JP_PORT);
120
        #5500;  // Wait until reset is complete
121
 
122
        while(1)
123
          begin
124
             #1;
125
             $jp_in(memory);  // This will not change memory[][] if no command has been sent from jp
126
             if(memory[4])  // was memory[0][4]
127
               begin
128
                  in_word_r = memory[3:0];
129
                  memory = memory & 4'b1111;
130
                  clk_count = 6'b000000;  // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
131
               end
132
          end
133
     end
134
 
135
 
136
 
137
   // Send the output bit to the upper layer
138
   always @ (P_TDO)
139
     begin
140
        $jp_out(P_TDO);
141
     end
142
 
143
 
144
   assign P_TCK  = in_word_r[0];
145
   assign P_TRST = in_word_r[1];
146
   assign P_TDI  = in_word_r[2];
147
   assign P_TMS  = in_word_r[3];
148
 
149
 
150
   // Send timeouts / wait periods to the upper layer
151
   always @ (posedge SYS_CLK)
152
     begin
153
        if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
154
        else if(clk_count == `TIMEOUT_COUNT) begin
155
           $jp_wait_time();
156
           clk_count[5:0] = clk_count[5:0] + 1;
157
        end
158
        // else it's already timed out, don't do anything
159
     end
160
 
161
endmodule
162
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.