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104 |
rfajardo |
VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
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VHDL_PROJECTS = altera_virtual_jtag.prj
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| 3 |
85 |
rfajardo |
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104 |
rfajardo |
PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS)
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85 |
rfajardo |
SRC_DIR = src
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SCRIPTS_DIR = scripts
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SIMULATION_DIR = sim
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XILINX_DIR = xilinx
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ALTERA_DIR = altera
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| 12 |
104 |
rfajardo |
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
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SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
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| 14 |
85 |
rfajardo |
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
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XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
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95 |
javieralso |
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
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| 17 |
85 |
rfajardo |
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104 |
rfajardo |
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
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| 19 |
85 |
rfajardo |
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clean:
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| 21 |
104 |
rfajardo |
rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
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| 22 |
85 |
rfajardo |
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| 23 |
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$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
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bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
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| 26 |
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$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
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bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule
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| 28 |
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| 29 |
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$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj
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bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
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| 31 |
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| 32 |
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$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
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bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
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| 34 |
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| 35 |
95 |
javieralso |
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
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bash $(SCRIPTS_DIR)/altprj.sh $^ $@
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| 37 |
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| 38 |
104 |
rfajardo |
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
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| 39 |
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cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
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| 40 |
85 |
rfajardo |
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| 41 |
104 |
rfajardo |
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)
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| 42 |
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cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src
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| 43 |
85 |
rfajardo |
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| 44 |
104 |
rfajardo |
$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj
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| 45 |
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bash $(SCRIPTS_DIR)/simverilog.sh $^ $@
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| 46 |
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| 47 |
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$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj
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| 48 |
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bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@
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| 49 |
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