| 1 |
104 |
rfajardo |
VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
|
| 2 |
|
|
VHDL_PROJECTS = altera_virtual_jtag.prj
|
| 3 |
85 |
rfajardo |
|
| 4 |
104 |
rfajardo |
PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS)
|
| 5 |
85 |
rfajardo |
SRC_DIR = src
|
| 6 |
|
|
SCRIPTS_DIR = scripts
|
| 7 |
|
|
|
| 8 |
|
|
SIMULATION_DIR = sim
|
| 9 |
|
|
XILINX_DIR = xilinx
|
| 10 |
|
|
ALTERA_DIR = altera
|
| 11 |
|
|
|
| 12 |
104 |
rfajardo |
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
|
| 13 |
|
|
SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
|
| 14 |
141 |
rfajardo |
|
| 15 |
85 |
rfajardo |
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
|
| 16 |
|
|
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
|
| 17 |
|
|
|
| 18 |
141 |
rfajardo |
ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS))))
|
| 19 |
|
|
ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS))))
|
| 20 |
85 |
rfajardo |
|
| 21 |
141 |
rfajardo |
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES)
|
| 22 |
|
|
|
| 23 |
85 |
rfajardo |
clean:
|
| 24 |
141 |
rfajardo |
rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.vprj $(ALTERA_DIR)/*.vhdprj
|
| 25 |
85 |
rfajardo |
|
| 26 |
141 |
rfajardo |
|
| 27 |
85 |
rfajardo |
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
|
| 28 |
|
|
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
|
| 29 |
|
|
|
| 30 |
|
|
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
|
| 31 |
|
|
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule
|
| 32 |
|
|
|
| 33 |
|
|
$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj
|
| 34 |
|
|
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
|
| 35 |
|
|
|
| 36 |
|
|
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
|
| 37 |
|
|
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
|
| 38 |
|
|
|
| 39 |
95 |
javieralso |
|
| 40 |
141 |
rfajardo |
$(ALTERA_DIR)/%.vprj: $(SRC_DIR)/%.prj
|
| 41 |
|
|
bash $(SCRIPTS_DIR)/altvprj.sh $^ $@
|
| 42 |
|
|
|
| 43 |
|
|
$(ALTERA_DIR)/%.vhdprj: $(SRC_DIR)/%.prj
|
| 44 |
|
|
bash $(SCRIPTS_DIR)/altvhdprj.sh $^ $@
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
104 |
rfajardo |
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
|
| 48 |
|
|
cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
|
| 49 |
85 |
rfajardo |
|
| 50 |
104 |
rfajardo |
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)
|
| 51 |
|
|
cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src
|
| 52 |
85 |
rfajardo |
|
| 53 |
104 |
rfajardo |
$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj
|
| 54 |
|
|
bash $(SCRIPTS_DIR)/simverilog.sh $^ $@
|
| 55 |
|
|
|
| 56 |
|
|
$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj
|
| 57 |
|
|
bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@
|
| 58 |
|
|
|
