URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [prj/] [Makefile] - Blame information for rev 87
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
85 |
rfajardo |
PROJECTS = minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
|
| 2 |
|
|
|
| 3 |
|
|
SRC_DIR = src
|
| 4 |
|
|
SCRIPTS_DIR = scripts
|
| 5 |
|
|
|
| 6 |
|
|
SIMULATION_DIR = sim
|
| 7 |
|
|
XILINX_DIR = xilinx
|
| 8 |
|
|
ALTERA_DIR = altera
|
| 9 |
|
|
|
| 10 |
|
|
SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS))))
|
| 11 |
|
|
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
|
| 12 |
|
|
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
|
| 13 |
|
|
|
| 14 |
|
|
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES)
|
| 15 |
|
|
|
| 16 |
|
|
clean:
|
| 17 |
|
|
rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst
|
| 18 |
|
|
|
| 19 |
|
|
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
|
| 20 |
|
|
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
|
| 21 |
|
|
|
| 22 |
|
|
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
|
| 23 |
|
|
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule
|
| 24 |
|
|
|
| 25 |
|
|
$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj
|
| 26 |
|
|
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
|
| 27 |
|
|
|
| 28 |
|
|
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
|
| 29 |
|
|
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
|
| 30 |
|
|
|
| 31 |
|
|
$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES)
|
| 32 |
|
|
cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src
|
| 33 |
|
|
|
| 34 |
|
|
$(SIMULATION_DIR)/%.src: $(SRC_DIR)/%.prj
|
| 35 |
|
|
bash $(SCRIPTS_DIR)/simprj.sh $^ $@
|
| 36 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.