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Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [src/] [adbg_top.prj] - Blame information for rev 167

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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
PROJECT_SRC=(adbg_crc32.v
adbg_defines.v
adbg_jsp_biu.v
adbg_jsp_module.v
adbg_or1k_biu.v
adbg_or1k_defines.v
adbg_or1k_module.v
adbg_or1k_status_reg.v
adbg_top.v
adbg_wb_biu.v
adbg_wb_defines.v
adbg_wb_module.v
bytefifo.v
syncflop.v
syncreg.v)

Line No.	Rev	Author	Line
1	85	rfajardo	`PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog`
2	158	rfajardo	`PROJECT_SRC=(adbg_crc32.v`
3	85	rfajardo	`adbg_defines.v`
4	158	rfajardo	`adbg_jsp_biu.v`
5			`adbg_jsp_module.v`
6	85	rfajardo	`adbg_or1k_biu.v`
7			`adbg_or1k_defines.v`
8	158	rfajardo	`adbg_or1k_module.v`
9	85	rfajardo	`adbg_or1k_status_reg.v`
10	158	rfajardo	`adbg_top.v`
11			`adbg_wb_biu.v`
12			`adbg_wb_defines.v`
13			`adbg_wb_module.v`
14			`bytefifo.v`
15			`syncflop.v`
16			`syncreg.v)`

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[/] [minsoc/] [trunk/] [prj/] [src/] [adbg_top.prj] - Blame information for rev 167