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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_bench.prj] - Blame information for rev 145

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PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
PROJECT_SRC=(minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v)
 

Line No.	Rev	Author	Line
1	88	rfajardo	`PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)`
2			`PROJECT_SRC=(minsoc_bench_defines.v`
3			`minsoc_bench.v`
4			`minsoc_memory_model.v`
5			`dbg_comm_vpi.v`
6			`fpga_memory_primitives.v`
7			`timescale.v)`
8

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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_bench.prj] - Blame information for rev 145