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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 174

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PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
PROJECT_SRC=(minsoc_defines.v
timescale.v
interconnect_defines.v
minsoc_top.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_onchip_ram_top.v
minsoc_clock_manager.v
altera_pll.v
xilinx_dcm.v
minsoc_xilinx_internal_jtag.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v)
 

Line No.	Rev	Author	Line
1	89	rfajardo	`PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)`
2	85	rfajardo	`PROJECT_SRC=(minsoc_defines.v`
3			`timescale.v`
4	158	rfajardo	`interconnect_defines.v`
5	85	rfajardo	`minsoc_top.v`
6	88	rfajardo	`minsoc_tc_top.v`
7			`minsoc_onchip_ram.v`
8			`minsoc_onchip_ram_top.v`
9			`minsoc_clock_manager.v`
10			`altera_pll.v`
11			`xilinx_dcm.v`
12			`minsoc_xilinx_internal_jtag.v`
13	85	rfajardo	`spi_top.v`
14			`spi_defines.v`
15			`spi_shift.v`
16			`spi_clgen.v`
17	88	rfajardo	`OR1K_startup_generic.v)`
18

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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 174