URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 86

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PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)
PROJECT_SRC=(minsoc_defines.v
minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v
minsoc_top.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_clock_manager.v
minsoc_onchip_ram_top.v)

Line No.	Rev	Author	Line
1	85	rfajardo	`PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)`
2			`PROJECT_SRC=(minsoc_defines.v`
3			`minsoc_bench_defines.v`
4			`minsoc_bench.v`
5			`minsoc_memory_model.v`
6			`dbg_comm_vpi.v`
7			`fpga_memory_primitives.v`
8			`timescale.v`
9			`minsoc_top.v`
10			`spi_top.v`
11			`spi_defines.v`
12			`spi_shift.v`
13			`spi_clgen.v`
14			`OR1K_startup_generic.v`
15			`minsoc_tc_top.v`
16			`minsoc_onchip_ram.v`
17			`minsoc_clock_manager.v`
18			`minsoc_onchip_ram_top.v)`

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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 86