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[/] [minsoc/] [trunk/] [prj/] [src/] [or1200_top.prj] - Blame information for rev 96

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Line No. Rev Author Line
1 85 rfajardo 
PROJECT_DIR=rtl/verilog/or1200/rtl/verilog
2 
PROJECT_SRC=(or1200_spram_512x20.v
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or1200_spram_64x24.v
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or1200_du.v
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or1200_spram_2048x32_bw.v
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or1200_rf.v
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or1200_alu.v
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or1200_dmmu_top.v
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or1200_lsu.v
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or1200_spram_1024x32.v
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or1200_dc_top.v
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or1200_cpu.v
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or1200_gmultp2_32x32.v
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or1200_immu_top.v
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or1200_dpram_256x32.v
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or1200_tt.v
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or1200_iwb_biu.v
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or1200_rfram_generic.v
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or1200_dc_tag.v
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or1200_spram_2048x8.v
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or1200_immu_tlb.v
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or1200_ic_tag.v
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or1200_spram_64x14.v
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or1200_spram_32x24.v
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or1200_dpram_32x32.v
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or1200_xcv_ram32x8d.v
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or1200_spram_1024x8.v
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or1200_mem2reg.v
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or1200_pm.v
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or1200_spram_256x21.v
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or1200_operandmuxes.v
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or1200_pic.v
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or1200_cfgr.v
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or1200_if.v
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or1200_qmem_top.v
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or1200_genpc.v
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or1200_defines.v
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or1200_wbmux.v
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or1200_ic_ram.v
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or1200_dmmu_tlb.v
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or1200_sb_fifo.v
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or1200_sprs.v
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or1200_tpram_32x32.v
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or1200_ctrl.v
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or1200_sb.v
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or1200_mult_mac.v
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or1200_ic_fsm.v
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or1200_amultp2_32x32.v
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or1200_reg2mem.v
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or1200_spram_2048x32.v
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or1200_except.v
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or1200_top.v
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or1200_ic_top.v
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or1200_dc_ram.v
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or1200_spram_1024x32_bw.v
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or1200_freeze.v
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or1200_spram_128x32.v
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or1200_dc_fsm.v
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or1200_wb_biu.v
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or1200_spram_64x22.v
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or1200_fpu.v
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or1200_spram.v
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or1200_spram_32_bw.v
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or1200_dpram.v)

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