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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [altera_pll.v] - Blame information for rev 70

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1 52 javieralso 
 
2 62 rfajardo 
`include "minsoc_defines.v"
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module altera_pll (
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        inclk0,
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        c0);
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        parameter FREQ_MULT = 1;
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        parameter FREQ_DIV = 1;
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        input     inclk0;
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        output    c0;
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`ifdef ARRIA_GX
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    localparam FAMILY = "Arria GX";
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`elsif ARRIA_II_GX
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    localparam FAMILY = "Arria II GX";
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`elsif CYCLONE_I
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    localparam FAMILY = "Cyclone I";
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`elsif CYCLONE_II
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    localparam FAMILY = "Cyclone II";
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`elsif CYCLONE_III
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    localparam FAMILY = "Cyclone III";
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`elsif CYCLONE_III_LS
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    localparam FAMILY = "Cyclone III LS";
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`elsif CYCLONE_IV_E
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    localparam FAMILY = "Cyclone IV E";
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`elsif CYCLONE_IV_GS
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    localparam FAMILY = "Cyclone IV GS";
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`elsif MAX_II
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    localparam FAMILY = "MAX II";
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`elsif MAX_V
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    localparam FAMILY = "MAX V";
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`elsif MAX3000A
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    localparam FAMILY = "MAX3000A";
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`elsif MAX7000AE
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    localparam FAMILY = "MAX7000AE";
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`elsif MAX7000B
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    localparam FAMILY = "MAX7000B";
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`elsif MAX7000S
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    localparam FAMILY = "MAX7000S";
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`elsif STRATIX
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    localparam FAMILY = "Stratix";
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`elsif STRATIX_II
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    defapram systemPll.FAMILY = "Stratix II";
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`elsif STRATIX_II_GX
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    localparam FAMILY = "Stratix II GX";
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`elsif STRATIX_III
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    localparam FAMILY = "Stratix III"
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`endif
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        wire [4:0] sub_wire0;
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        wire [0:0] sub_wire4 = 1'h0;
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        wire [0:0] sub_wire1 = sub_wire0[0:0];
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        wire  c0 = sub_wire1;
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        wire  sub_wire2 = inclk0;
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        wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
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`ifdef ALTERA_FPGA
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        altpll  altpll_component (
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                                .inclk (sub_wire3),
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                                .clk (sub_wire0),
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                                .activeclock (),
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                                .areset (1'b0),
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                                .clkbad (),
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                                .clkena ({6{1'b1}}),
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                                .clkloss (),
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                                .clkswitch (1'b0),
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                                .configupdate (1'b0),
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                                .enable0 (),
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                                .enable1 (),
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                                .extclk (),
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                                .extclkena ({4{1'b1}}),
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                                .fbin (1'b1),
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                                .fbmimicbidir (),
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                                .fbout (),
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                                .fref (),
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                                .icdrclk (),
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                                .locked (),
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                                .pfdena (1'b1),
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                                .phasecounterselect ({4{1'b1}}),
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                                .phasedone (),
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                                .phasestep (1'b1),
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                                .phaseupdown (1'b1),
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                                .pllena (1'b1),
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                                .scanaclr (1'b0),
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                                .scanclk (1'b0),
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                                .scanclkena (1'b1),
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                                .scandata (1'b0),
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                                .scandataout (),
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                                .scandone (),
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                                .scanread (1'b0),
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                                .scanwrite (1'b0),
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                                .sclkout0 (),
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                                .sclkout1 (),
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                                .vcooverrange (),
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                                .vcounderrange ());
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        defparam
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                altpll_component.bandwidth_type = "AUTO",
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                altpll_component.clk0_divide_by = FREQ_DIV,
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                altpll_component.clk0_duty_cycle = 50,
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                altpll_component.clk0_multiply_by = FREQ_MULT,
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                altpll_component.clk0_phase_shift = "0",
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                altpll_component.compensate_clock = "CLK0",
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                altpll_component.inclk0_input_frequency = 20000,
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                altpll_component.intended_device_family = FAMILY,
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                altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
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                altpll_component.lpm_type = "altpll",
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                altpll_component.operation_mode = "NORMAL",
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                altpll_component.pll_type = "AUTO",
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                altpll_component.port_activeclock = "PORT_UNUSED",
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                altpll_component.port_areset = "PORT_UNUSED",
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                altpll_component.port_clkbad0 = "PORT_UNUSED",
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                altpll_component.port_clkbad1 = "PORT_UNUSED",
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                altpll_component.port_clkloss = "PORT_UNUSED",
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                altpll_component.port_clkswitch = "PORT_UNUSED",
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                altpll_component.port_configupdate = "PORT_UNUSED",
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                altpll_component.port_fbin = "PORT_UNUSED",
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                altpll_component.port_inclk0 = "PORT_USED",
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                altpll_component.port_inclk1 = "PORT_UNUSED",
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                altpll_component.port_locked = "PORT_UNUSED",
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                altpll_component.port_pfdena = "PORT_UNUSED",
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                altpll_component.port_phasecounterselect = "PORT_UNUSED",
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                altpll_component.port_phasedone = "PORT_UNUSED",
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                altpll_component.port_phasestep = "PORT_UNUSED",
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                altpll_component.port_phaseupdown = "PORT_UNUSED",
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                altpll_component.port_pllena = "PORT_UNUSED",
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                altpll_component.port_scanaclr = "PORT_UNUSED",
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                altpll_component.port_scanclk = "PORT_UNUSED",
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                altpll_component.port_scanclkena = "PORT_UNUSED",
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                altpll_component.port_scandata = "PORT_UNUSED",
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                altpll_component.port_scandataout = "PORT_UNUSED",
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                altpll_component.port_scandone = "PORT_UNUSED",
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                altpll_component.port_scanread = "PORT_UNUSED",
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                altpll_component.port_scanwrite = "PORT_UNUSED",
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                altpll_component.port_clk0 = "PORT_USED",
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                altpll_component.port_clk1 = "PORT_UNUSED",
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                altpll_component.port_clk2 = "PORT_UNUSED",
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                altpll_component.port_clk3 = "PORT_UNUSED",
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                altpll_component.port_clk4 = "PORT_UNUSED",
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                altpll_component.port_clk5 = "PORT_UNUSED",
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                altpll_component.port_clkena0 = "PORT_UNUSED",
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                altpll_component.port_clkena1 = "PORT_UNUSED",
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                altpll_component.port_clkena2 = "PORT_UNUSED",
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                altpll_component.port_clkena3 = "PORT_UNUSED",
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                altpll_component.port_clkena4 = "PORT_UNUSED",
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                altpll_component.port_clkena5 = "PORT_UNUSED",
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                altpll_component.port_extclk0 = "PORT_UNUSED",
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                altpll_component.port_extclk1 = "PORT_UNUSED",
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                altpll_component.port_extclk2 = "PORT_UNUSED",
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                altpll_component.port_extclk3 = "PORT_UNUSED",
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                altpll_component.width_clock = 5;
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`endif
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endmodule
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