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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [interconnect_defines.v] - Blame information for rev 164

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//
// Interrupts
//
`define APP_INT_RES1        1:0
`define APP_INT_UART        2
`define APP_INT_RES2        3
`define APP_INT_ETH         4
`define APP_INT_PS2         5
`define APP_INT_JSP         6
`define APP_INT_RES3        19:7
 
//
// Address map
//
`define APP_ADDR_DEC_W      8
`define APP_ADDR_SRAM       `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH      `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W     4
`define APP_ADDR_PERIP      `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI        `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH        `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO      `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART       `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2        `APP_ADDR_DEC_W'h94
`define APP_ADDR_JSP        `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2       `APP_ADDR_DEC_W'h9f

Line No.	Rev	Author	Line
1	158	rfajardo	`//`
2			`// Interrupts`
3			`//`
4			`define APP_INT_RES1 1:0
5			`define APP_INT_UART 2
6			`define APP_INT_RES2 3
7			`define APP_INT_ETH 4
8			`define APP_INT_PS2 5
9			`define APP_INT_JSP 6
10			`define APP_INT_RES3 19:7
11
12			`//`
13			`// Address map`
14			`//`
15			`define APP_ADDR_DEC_W 8
16			`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
17			`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
18			`define APP_ADDR_DECP_W 4
19			`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
20			`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
21			`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
22			`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
23			`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
24			`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
25			`define APP_ADDR_JSP `APP_ADDR_DEC_W'h9e
26			`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [interconnect_defines.v] - Blame information for rev 164