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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 18

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`include "minsoc_defines.v"
 
module minsoc_clock_manager(
        clk_i,
        clk_o
);
 
// 
// Parameters 
// 
parameter    divisor = 5;
 
input clk_i;
output clk_o;
 
`ifdef NO_CLOCK_DIVISION
assign clk_o = clk_i;
 
`elsif GENERIC_CLOCK_DIVISION
reg [31:0] clock_divisor;
reg clk_int;
always @ (posedge clk_i)
begin
        clock_divisor <= clock_divisor + 1'b1;
        if ( clock_divisor >= divisor/2 - 1 ) begin
                clk_int <= ~clk_int;
                clock_divisor <= 32'h0000_0000;
        end
end
assign clk_o = clk_int;
`elsif FPGA_CLOCK_DIVISION
 
`ifdef ALTERA_FPGA
reg [31:0] clock_divisor;
reg clk_int;
always @ (posedge clk_i)
begin
        clock_divisor <= clock_divisor + 1'b1;
        if ( clock_divisor >= divisor/2 - 1 ) begin
                clk_int <= ~clk_int;
                clock_divisor <= 32'h0000_0000;
        end
end
assign clk_o = clk_int;
 
`elsif XILINX_FPGA
 
`ifdef SPARTAN2
        `define MINSOC_DLL
`elsif VIRTEX
        `define MINSOC_DLL
`endif  // !SPARTAN2/VIRTEX
 
`ifdef SPARTAN3
        `define MINSOC_DCM
`elsif VIRTEX2
        `define MINSOC_DCM
`endif  // !SPARTAN3/VIRTEX2
 
`ifdef SPARTAN3E
        `define MINSOC_DCM_SP
`elsif SPARTAN3A
        `define MINSOC_DCM_SP
`endif  // !SPARTAN3E/SPARTAN3A
 
`ifdef VIRTEX4
        `define MINSOC_DCM_ADV
        `define MINSOC_DCM_COMPONENT "VIRTEX4"
`elsif VIRTEX5
        `define MINSOC_DCM_ADV
        `define MINSOC_DCM_COMPONENT "VIRTEX5"
`endif  // !VIRTEX4/VIRTEX5
 
wire CLKIN_IN;
wire CLKDV_OUT;
 
assign CLKIN_IN = clk_i;
assign clk_o = CLKDV_OUT;
 
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKDV_BUF;
 
IBUFG CLKIN_IBUFG_INST (
        .I(CLKIN_IN),
        .O(CLKIN_IBUFG)
);
 
BUFG CLK0_BUFG_INST (
        .I(CLK0_BUF),
        .O(CLKFB_IN)
);
 
BUFG CLKDV_BUFG_INST (
        .I(CLKDV_BUF),
        .O(CLKDV_OUT)
);
 
`ifdef MINSOC_DLL
 
CLKDLL #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .FACTORY_JF(16'hC080),                  // FACTORY JF Values
        .STARTUP_WAIT("FALSE")                  // Delay config DONE until DLL LOCK, TRUE/FALSE
) CLKDLL_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DLL CLK output
        .CLK180(),                              // 180 degree DLL CLK output
        .CLK270(),                              // 270 degree DLL CLK output
        .CLK2X(),                               // 2X DLL CLK output
        .CLK90(),                               // 90 degree DLL CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DLL CLK out (CLKDV_DIVIDE)
        .LOCKED(),                              // DLL LOCK status output
        .CLKFB(CLKFB_IN),                       // DLL clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DLL)
        .RST(1'b0)                              // DLL asynchronous reset input
);
 
`elsif MINSOC_DCM
 
DCM #(
        .SIM_MODE("SAFE"),                      // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .FACTORY_JF(16'hC080),                  // FACTORY JF values
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .STATUS(),                              // 8-bit DCM status bits output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`elsif MINSOC_DCM_SP
 
DCM_SP #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(0.0),                     // Specify period of input clock
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift of NONE, FIXED or VARIABLE
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DLL_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, TRUE or FALSE
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 255
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .STATUS(),                              // 8-bit DCM status bits output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`elsif MINSOC_DCM_ADV
 
DCM_ADV #(
        .CLKDV_DIVIDE(divisor),                 // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                                                //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
        .CLKFX_DIVIDE(1),                       // Can be any integer from 1 to 32
        .CLKFX_MULTIPLY(4),                     // Can be any integer from 2 to 32
        .CLKIN_DIVIDE_BY_2("FALSE"),            // TRUE/FALSE to enable CLKIN divide by two feature
        .CLKIN_PERIOD(10.0),                    // Specify period of input clock in ns from 1.25 to 1000.00
        .CLKOUT_PHASE_SHIFT("NONE"),            // Specify phase shift mode of NONE, FIXED,
                                                // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
        .CLK_FEEDBACK("1X"),                    // Specify clock feedback of NONE, 1X or 2X
        .DCM_AUTOCALIBRATION("TRUE"),           // DCM calibration circuitry "TRUE"/"FALSE"
        .DCM_PERFORMANCE_MODE("MAX_SPEED"),     // Can be MAX_SPEED or MAX_RANGE
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),   // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                                //   an integer from 0 to 15
        .DFS_FREQUENCY_MODE("LOW"),             // HIGH or LOW frequency mode for frequency synthesis
        .DLL_FREQUENCY_MODE("LOW"),             // LOW, HIGH, or HIGH_SER frequency mode for DLL
        .DUTY_CYCLE_CORRECTION("TRUE"),         // Duty cycle correction, "TRUE"/"FALSE"
        .FACTORY_JF(16'hf0f0),                  // FACTORY JF value suggested to be set to 16’hf0f0
        .PHASE_SHIFT(0),                         // Amount of fixed phase shift from -255 to 1023
        .SIM_DEVICE(`MINSOC_DCM_COMPONENT),     // Set target device, "VIRTEX4" or "VIRTEX5"
        .STARTUP_WAIT("FALSE")                  // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
        .CLK0(CLK0_BUF),                        // 0 degree DCM CLK output
        .CLK180(),                              // 180 degree DCM CLK output
        .CLK270(),                              // 270 degree DCM CLK output
        .CLK2X(),                               // 2X DCM CLK output
        .CLK2X180(),                            // 2X, 180 degree DCM CLK out
        .CLK90(),                               // 90 degree DCM CLK output
        .CLKDV(CLKDV_BUF),                      // Divided DCM CLK out (CLKDV_DIVIDE)
        .CLKFX(),                               // DCM CLK synthesis out (M/D)
        .CLKFX180(),                            // 180 degree CLK synthesis out
        .DO(),                                  // 16-bit data output for Dynamic Reconfiguration Port (DRP)
        .DRDY(),                                // Ready output signal from the DRP
        .LOCKED(),                              // DCM LOCK status output
        .PSDONE(),                              // Dynamic phase adjust done output
        .CLKFB(CLKFB_IN),                       // DCM clock feedback
        .CLKIN(CLKIN_IBUFG),                    // Clock input (from IBUFG, BUFG or DCM)
        .DADDR(7'h00),                          // 7-bit address for the DRP
        .DCLK(1'b0),                            // Clock for the DRP
        .DEN(1'b0),                             // Enable input for the DRP
        .DI(16'h0000),                          // 16-bit data input for the DRP
        .DWE(1'b0),                             // Active high allows for writing configuration memory
        .PSCLK(1'b0),                           // Dynamic phase adjust clock input
        .PSEN(1'b0),                            // Dynamic phase adjust enable input
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
);
 
`endif  // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
`endif  // !ALTERA_FPGA/XILINX_FPGA
`endif  // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
 
 
endmodule

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	2	rfajardo
2			`include "minsoc_defines.v"
3
4			`module minsoc_clock_manager(`
5			`clk_i,`
6			`clk_o`
7			`);`
8
9			`//`
10			`// Parameters`
11			`//`
12			`parameter divisor = 5;`
13
14			`input clk_i;`
15			`output clk_o;`
16
17			`ifdef NO_CLOCK_DIVISION
18			`assign clk_o = clk_i;`
19
20			`elsif GENERIC_CLOCK_DIVISION
21			`reg [31:0] clock_divisor;`
22			`reg clk_int;`
23			`always @ (posedge clk_i)`
24			`begin`
25			`clock_divisor <= clock_divisor + 1'b1;`
26			`if ( clock_divisor >= divisor/2 - 1 ) begin`
27			`clk_int <= ~clk_int;`
28			`clock_divisor <= 32'h0000_0000;`
29			`end`
30			`end`
31			`assign clk_o = clk_int;`
32			`elsif FPGA_CLOCK_DIVISION
33
34			`ifdef ALTERA_FPGA
35			`reg [31:0] clock_divisor;`
36			`reg clk_int;`
37			`always @ (posedge clk_i)`
38			`begin`
39			`clock_divisor <= clock_divisor + 1'b1;`
40			`if ( clock_divisor >= divisor/2 - 1 ) begin`
41			`clk_int <= ~clk_int;`
42			`clock_divisor <= 32'h0000_0000;`
43			`end`
44			`end`
45			`assign clk_o = clk_int;`
46
47			`elsif XILINX_FPGA
48
49			`ifdef SPARTAN2
50			`define MINSOC_DLL
51			`elsif VIRTEX
52			`define MINSOC_DLL
53			`endif // !SPARTAN2/VIRTEX
54
55			`ifdef SPARTAN3
56			`define MINSOC_DCM
57			`elsif VIRTEX2
58			`define MINSOC_DCM
59			`endif // !SPARTAN3/VIRTEX2
60
61			`ifdef SPARTAN3E
62			`define MINSOC_DCM_SP
63			`elsif SPARTAN3A
64			`define MINSOC_DCM_SP
65			`endif // !SPARTAN3E/SPARTAN3A
66
67			`ifdef VIRTEX4
68			`define MINSOC_DCM_ADV
69			`define MINSOC_DCM_COMPONENT "VIRTEX4"
70			`elsif VIRTEX5
71			`define MINSOC_DCM_ADV
72			`define MINSOC_DCM_COMPONENT "VIRTEX5"
73			`endif // !VIRTEX4/VIRTEX5
74
75			`wire CLKIN_IN;`
76			`wire CLKDV_OUT;`
77
78			`assign CLKIN_IN = clk_i;`
79			`assign clk_o = CLKDV_OUT;`
80
81			`wire CLKIN_IBUFG;`
82			`wire CLK0_BUF;`
83			`wire CLKFB_IN;`
84			`wire CLKDV_BUF;`
85
86			`IBUFG CLKIN_IBUFG_INST (`
87			`.I(CLKIN_IN),`
88			`.O(CLKIN_IBUFG)`
89			`);`
90
91			`BUFG CLK0_BUFG_INST (`
92			`.I(CLK0_BUF),`
93			`.O(CLKFB_IN)`
94			`);`
95
96			`BUFG CLKDV_BUFG_INST (`
97			`.I(CLKDV_BUF),`
98			`.O(CLKDV_OUT)`
99			`);`
100
101			`ifdef MINSOC_DLL
102
103			`CLKDLL #(`
104			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0`
105			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
106			`.FACTORY_JF(16'hC080), // FACTORY JF Values`
107			`.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE`
108			`) CLKDLL_inst (`
109			`.CLK0(CLK0_BUF), // 0 degree DLL CLK output`
110			`.CLK180(), // 180 degree DLL CLK output`
111			`.CLK270(), // 270 degree DLL CLK output`
112			`.CLK2X(), // 2X DLL CLK output`
113			`.CLK90(), // 90 degree DLL CLK output`
114			`.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)`
115			`.LOCKED(), // DLL LOCK status output`
116			`.CLKFB(CLKFB_IN), // DLL clock feedback`
117			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)`
118			`.RST(1'b0) // DLL asynchronous reset input`
119			`);`
120
121			`elsif MINSOC_DCM
122
123			`DCM #(`
124			`.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details`
125			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
126			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
127			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
128			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
129			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
130			`.CLKIN_PERIOD(0.0), // Specify period of input clock`
131			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE`
132			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
133			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
134			`// an integer from 0 to 15`
135			`.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis`
136			`.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL`
137			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
138			`.FACTORY_JF(16'hC080), // FACTORY JF values`
139			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255`
140			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE`
141			`) DCM_inst (`
142			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
143			`.CLK180(), // 180 degree DCM CLK output`
144			`.CLK270(), // 270 degree DCM CLK output`
145			`.CLK2X(), // 2X DCM CLK output`
146			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
147			`.CLK90(), // 90 degree DCM CLK output`
148			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
149			`.CLKFX(), // DCM CLK synthesis out (M/D)`
150			`.CLKFX180(), // 180 degree CLK synthesis out`
151			`.LOCKED(), // DCM LOCK status output`
152			`.PSDONE(), // Dynamic phase adjust done output`
153			`.STATUS(), // 8-bit DCM status bits output`
154			`.CLKFB(CLKFB_IN), // DCM clock feedback`
155			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
156			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
157			`.PSEN(1'b0), // Dynamic phase adjust enable input`
158			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
159			`.RST(1'b0) // DCM asynchronous reset input`
160			`);`
161
162			`elsif MINSOC_DCM_SP
163
164			`DCM_SP #(`
165			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
166			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
167			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
168			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
169			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
170			`.CLKIN_PERIOD(0.0), // Specify period of input clock`
171			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE`
172			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
173			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
174			`// an integer from 0 to 15`
175			`.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL`
176			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE`
177			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255`
178			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE`
179			`) DCM_SP_inst (`
180			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
181			`.CLK180(), // 180 degree DCM CLK output`
182			`.CLK270(), // 270 degree DCM CLK output`
183			`.CLK2X(), // 2X DCM CLK output`
184			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
185			`.CLK90(), // 90 degree DCM CLK output`
186			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
187			`.CLKFX(), // DCM CLK synthesis out (M/D)`
188			`.CLKFX180(), // 180 degree CLK synthesis out`
189			`.LOCKED(), // DCM LOCK status output`
190			`.PSDONE(), // Dynamic phase adjust done output`
191			`.STATUS(), // 8-bit DCM status bits output`
192			`.CLKFB(CLKFB_IN), // DCM clock feedback`
193			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
194			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
195			`.PSEN(1'b0), // Dynamic phase adjust enable input`
196			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
197			`.RST(1'b0) // DCM asynchronous reset input`
198			`);`
199
200			`elsif MINSOC_DCM_ADV
201
202			`DCM_ADV #(`
203			`.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5`
204			`// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0`
205			`.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32`
206			`.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32`
207			`.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature`
208			`.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00`
209			`.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,`
210			`// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT`
211			`.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X`
212			`.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"`
213			`.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE`
214			`.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or`
215			`// an integer from 0 to 15`
216			`.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis`
217			`.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL`
218			`.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"`
219			`.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0`
220			`.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023`
221			.SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
222			`.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"`
223			`) DCM_ADV_inst (`
224			`.CLK0(CLK0_BUF), // 0 degree DCM CLK output`
225			`.CLK180(), // 180 degree DCM CLK output`
226			`.CLK270(), // 270 degree DCM CLK output`
227			`.CLK2X(), // 2X DCM CLK output`
228			`.CLK2X180(), // 2X, 180 degree DCM CLK out`
229			`.CLK90(), // 90 degree DCM CLK output`
230			`.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)`
231			`.CLKFX(), // DCM CLK synthesis out (M/D)`
232			`.CLKFX180(), // 180 degree CLK synthesis out`
233			`.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)`
234			`.DRDY(), // Ready output signal from the DRP`
235			`.LOCKED(), // DCM LOCK status output`
236			`.PSDONE(), // Dynamic phase adjust done output`
237			`.CLKFB(CLKFB_IN), // DCM clock feedback`
238			`.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)`
239			`.DADDR(7'h00), // 7-bit address for the DRP`
240			`.DCLK(1'b0), // Clock for the DRP`
241			`.DEN(1'b0), // Enable input for the DRP`
242			`.DI(16'h0000), // 16-bit data input for the DRP`
243			`.DWE(1'b0), // Active high allows for writing configuration memory`
244			`.PSCLK(1'b0), // Dynamic phase adjust clock input`
245			`.PSEN(1'b0), // Dynamic phase adjust enable input`
246			`.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement`
247			`.RST(1'b0) // DCM asynchronous reset input`
248			`);`
249
250			`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
251			`endif // !ALTERA_FPGA/XILINX_FPGA
252			`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
253
254
255			`endmodule`