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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 70

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`include "minsoc_defines.v"
 
module minsoc_clock_manager(
        clk_i,
        clk_o
);
 
// 
// Parameters 
// 
   parameter    divisor = 2;
 
input clk_i;
output clk_o;
 
`ifdef NO_CLOCK_DIVISION
assign clk_o = clk_i;
 
`elsif GENERIC_CLOCK_DIVISION
reg [31:0] clock_divisor;
reg clk_int;
always @ (posedge clk_i)
begin
        clock_divisor <= clock_divisor + 1'b1;
        if ( clock_divisor >= divisor/2 - 1 ) begin
                clk_int <= ~clk_int;
                clock_divisor <= 32'h0000_0000;
        end
end
assign clk_o = clk_int;
 
`elsif FPGA_CLOCK_DIVISION
`ifdef ALTERA_FPGA
altera_pll #
(
    .FREQ_DIV(divisor)
)
minsoc_altera_pll
(
    .inclk0(clk_i),
    .c0(clk_o)
);
 
`elsif XILINX_FPGA
xilinx_dcm #
(
    .divisor(divisor)
)
minsoc_xilinx_dcm
(
    .clk_i(clk_i),
    .clk_o(clk_o)
);
 
`endif  // !ALTERA_FPGA/XILINX_FPGA
`endif  // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
 
 
endmodule

Line No.	Rev	Author	Line
1	2	rfajardo
2			`include "minsoc_defines.v"
3
4			`module minsoc_clock_manager(`
5			`clk_i,`
6			`clk_o`
7			`);`
8
9			`//`
10			`// Parameters`
11			`//`
12	56	javieralso	`parameter divisor = 2;`
13
14	2	rfajardo	`input clk_i;`
15			`output clk_o;`
16
17			`ifdef NO_CLOCK_DIVISION
18			`assign clk_o = clk_i;`
19
20			`elsif GENERIC_CLOCK_DIVISION
21			`reg [31:0] clock_divisor;`
22			`reg clk_int;`
23			`always @ (posedge clk_i)`
24			`begin`
25			`clock_divisor <= clock_divisor + 1'b1;`
26			`if ( clock_divisor >= divisor/2 - 1 ) begin`
27			`clk_int <= ~clk_int;`
28			`clock_divisor <= 32'h0000_0000;`
29			`end`
30			`end`
31			`assign clk_o = clk_int;`
32	62	rfajardo
33	2	rfajardo	`elsif FPGA_CLOCK_DIVISION
34	62	rfajardo	`ifdef ALTERA_FPGA
35			`altera_pll #`
36			`(`
37			`.FREQ_DIV(divisor)`
38			`)`
39			`minsoc_altera_pll`
40			`(`
41			`.inclk0(clk_i),`
42			`.c0(clk_o)`
43			`);`
44	52	javieralso
45	2	rfajardo	`elsif XILINX_FPGA
46	62	rfajardo	`xilinx_dcm #`
47			`(`
48			`.divisor(divisor)`
49			`)`
50			`minsoc_xilinx_dcm`
51			`(`
52			`.clk_i(clk_i),`
53			`.clk_o(clk_o)`
54	2	rfajardo	`);`
55
56			`endif // !ALTERA_FPGA/XILINX_FPGA
57			`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
58
59
60			`endmodule`

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Blame information for rev 70