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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [spi_shift.v] - Blame information for rev 46

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_shift.v                                                 ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "spi_defines.v"
`include "timescale.v"
 
module spi_flash_shift
  (
   clk, rst, latch, byte_sel, len, go,
   pos_edge, neg_edge,
   lsb, rx_negedge, tx_negedge,
   tip, last,
   p_in, p_out, s_clk, s_in, s_out);
 
  parameter Tp = 1;
 
   input                          clk;          // system clock
   input                          rst;          // reset
   input                          latch;        // latch signal for storing the data in shift register
   input [3:0]                     byte_sel;     // byte select signals for storing the data in shift register
   input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
   input                          lsb;          // lbs first on the line
   input                          tx_negedge;
   input                          rx_negedge;
   input                          go;           // start stansfer
   input                          pos_edge;     // recognize posedge of sclk
   input                          neg_edge;     // recognize negedge of sclk
   output                         tip;          // transfer in progress
   output                         last;         // last bit
   input [31:0]            p_in;         // parallel in
   output [`SPI_MAX_CHAR-1:0]      p_out;        // parallel out
   input                          s_clk;        // serial clock
   input                          s_in;         // serial in
   output                         s_out;        // serial out
 
   reg                            s_out;
   reg                            tip;
 
   reg [`SPI_CHAR_LEN_BITS:0]      cnt;          // data bit count
   reg [`SPI_MAX_CHAR-1:0]         data;         // shift register
   wire [`SPI_CHAR_LEN_BITS:0]     tx_bit_pos;   // next bit position
   wire [`SPI_CHAR_LEN_BITS:0]     rx_bit_pos;   // next bit position
   wire                           rx_clk;       // rx clock enable
   wire                           tx_clk;       // tx clock enable
 
 
   assign p_out = data;
 
   assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
   assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
 
  assign last = !(|cnt);
 
  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
 
  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
 
  // Character bit counter
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
    else
      begin
        if(tip)
          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
        else
          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
      end
  end
 
  // Transfer in progress
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      tip <= #Tp 1'b0;
  else if(go && ~tip)
    tip <= #Tp 1'b1;
  else if(tip && last && pos_edge)
    tip <= #Tp 1'b0;
  end
 
  // Sending bits to the line
  always @(posedge clk or posedge rst)
  begin
    if (rst)
      s_out   <= #Tp 1'b0;
    else
      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
  end
 
   // Receiving bits from the line
   always @(posedge clk or posedge rst)
     if (rst)
       data   <= #Tp `SPI_CHAR_RST;
     else
       if (latch & !tip)
         begin
            if (byte_sel[0])
              data[7:0] <= #Tp p_in[7:0];
            if (byte_sel[1])
              data[15:8] <= #Tp p_in[15:8];
            if (byte_sel[2])
              data[23:16] <= #Tp p_in[23:16];
            if (byte_sel[3])
              data[31:24] <= #Tp p_in[31:24];
         end
       else
         data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rfajardo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_shift.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`include "spi_defines.v"
42			`include "timescale.v"
43
44			`module spi_flash_shift`
45			`(`
46			`clk, rst, latch, byte_sel, len, go,`
47			`pos_edge, neg_edge,`
48			`lsb, rx_negedge, tx_negedge,`
49			`tip, last,`
50			`p_in, p_out, s_clk, s_in, s_out);`
51
52			`parameter Tp = 1;`
53
54			`input clk; // system clock`
55			`input rst; // reset`
56			`input latch; // latch signal for storing the data in shift register`
57			`input [3:0] byte_sel; // byte select signals for storing the data in shift register`
58			input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
59			`input lsb; // lbs first on the line`
60			`input tx_negedge;`
61			`input rx_negedge;`
62			`input go; // start stansfer`
63			`input pos_edge; // recognize posedge of sclk`
64			`input neg_edge; // recognize negedge of sclk`
65			`output tip; // transfer in progress`
66			`output last; // last bit`
67			`input [31:0] p_in; // parallel in`
68			output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
69			`input s_clk; // serial clock`
70			`input s_in; // serial in`
71			`output s_out; // serial out`
72
73			`reg s_out;`
74			`reg tip;`
75
76			reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
77			reg [`SPI_MAX_CHAR-1:0] data; // shift register
78			wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
79			wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
80			`wire rx_clk; // rx clock enable`
81			`wire tx_clk; // tx clock enable`
82
83
84			`assign p_out = data;`
85
86			assign tx_bit_pos = lsb ? {!(\|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
87			assign rx_bit_pos = lsb ? {!(\|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
88
89			`assign last = !(\|cnt);`
90
91			`assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last \|\| s_clk);`
92
93			`assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;`
94
95			`// Character bit counter`
96			`always @(posedge clk or posedge rst)`
97			`begin`
98			`if(rst)`
99			cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
100			`else`
101			`begin`
102			`if(tip)`
103			cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
104			`else`
105			cnt <= #Tp !(\|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
106			`end`
107			`end`
108
109			`// Transfer in progress`
110			`always @(posedge clk or posedge rst)`
111			`begin`
112			`if(rst)`
113			`tip <= #Tp 1'b0;`
114			`else if(go && ~tip)`
115			`tip <= #Tp 1'b1;`
116			`else if(tip && last && pos_edge)`
117			`tip <= #Tp 1'b0;`
118			`end`
119
120			`// Sending bits to the line`
121			`always @(posedge clk or posedge rst)`
122			`begin`
123			`if (rst)`
124			`s_out <= #Tp 1'b0;`
125			`else`
126			s_out <= #Tp (tx_clk \|\| !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
127			`end`
128
129			`// Receiving bits from the line`
130			`always @(posedge clk or posedge rst)`
131			`if (rst)`
132			data <= #Tp `SPI_CHAR_RST;
133			`else`
134			`if (latch & !tip)`
135			`begin`
136			`if (byte_sel[0])`
137			`data[7:0] <= #Tp p_in[7:0];`
138			`if (byte_sel[1])`
139			`data[15:8] <= #Tp p_in[15:8];`
140			`if (byte_sel[2])`
141			`data[23:16] <= #Tp p_in[23:16];`
142			`if (byte_sel[3])`
143			`data[31:24] <= #Tp p_in[31:24];`
144			`end`
145			`else`
146			data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
147
148			`endmodule`
149

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [spi_shift.v] - Blame information for rev 46